The Experts below are selected from a list of 151935 Experts worldwide ranked by ideXlab platform
K.l. Young - One of the best experts on this subject based on the ideXlab platform.
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field configurable test structure array fc tsa enabling design for Monitor model and manufacturability
IEEE Transactions on Semiconductor Manufacturing, 2008Co-Authors: Kelvin Y.y. Doong, L.j. Hung, T J Bordelon, Chienchih Liao, S P S Ho, Sunnys Hsieh, K.l. YoungAbstract:This paper describes a common framework of test chip design for logic technology development and routine Process Monitoring, referred to as a field-configurable test structure array (FC-TSA), which can accommodate and test various types of test structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-test within the test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various test structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40 x 20 FC-TSA has been implemented by utilizing a state-of-the-art logic Process to demonstrate design feasibility. The measurements of a set of transistor and Process Monitor test structures are reviewed and corresponding models discussed.
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field configurable test structure array fc tsa enabling design for Monitor model and manufacturability
International Conference on Microelectronic Test Structures, 2006Co-Authors: Kelvin Y.y. Doong, L.j. Hung, Sunnys Hsieh, J Bordelon, Kehjeng Chang, C C Liao, R S Ho, K.l. YoungAbstract:This work is designated to provide a common frame work of test chip design for technology development and Process routine Monitor, called as field-configurable test structure array (FC-TSA), which can accommodate and test the various types of test structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-test in a test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various test structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array test structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic Process to demonstrate the design feasibility. The measurements of transistor set and Process Monitor test structures are reviewed and corresponding models are discussed.
Kelvin Y.y. Doong - One of the best experts on this subject based on the ideXlab platform.
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field configurable test structure array fc tsa enabling design for Monitor model and manufacturability
IEEE Transactions on Semiconductor Manufacturing, 2008Co-Authors: Kelvin Y.y. Doong, L.j. Hung, T J Bordelon, Chienchih Liao, S P S Ho, Sunnys Hsieh, K.l. YoungAbstract:This paper describes a common framework of test chip design for logic technology development and routine Process Monitoring, referred to as a field-configurable test structure array (FC-TSA), which can accommodate and test various types of test structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-test within the test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various test structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40 x 20 FC-TSA has been implemented by utilizing a state-of-the-art logic Process to demonstrate design feasibility. The measurements of a set of transistor and Process Monitor test structures are reviewed and corresponding models discussed.
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field configurable test structure array fc tsa enabling design for Monitor model and manufacturability
International Conference on Microelectronic Test Structures, 2006Co-Authors: Kelvin Y.y. Doong, L.j. Hung, Sunnys Hsieh, J Bordelon, Kehjeng Chang, C C Liao, R S Ho, K.l. YoungAbstract:This work is designated to provide a common frame work of test chip design for technology development and Process routine Monitor, called as field-configurable test structure array (FC-TSA), which can accommodate and test the various types of test structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-test in a test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various test structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array test structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic Process to demonstrate the design feasibility. The measurements of transistor set and Process Monitor test structures are reviewed and corresponding models are discussed.
Sunnys Hsieh - One of the best experts on this subject based on the ideXlab platform.
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field configurable test structure array fc tsa enabling design for Monitor model and manufacturability
IEEE Transactions on Semiconductor Manufacturing, 2008Co-Authors: Kelvin Y.y. Doong, L.j. Hung, T J Bordelon, Chienchih Liao, S P S Ho, Sunnys Hsieh, K.l. YoungAbstract:This paper describes a common framework of test chip design for logic technology development and routine Process Monitoring, referred to as a field-configurable test structure array (FC-TSA), which can accommodate and test various types of test structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-test within the test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various test structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40 x 20 FC-TSA has been implemented by utilizing a state-of-the-art logic Process to demonstrate design feasibility. The measurements of a set of transistor and Process Monitor test structures are reviewed and corresponding models discussed.
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field configurable test structure array fc tsa enabling design for Monitor model and manufacturability
International Conference on Microelectronic Test Structures, 2006Co-Authors: Kelvin Y.y. Doong, L.j. Hung, Sunnys Hsieh, J Bordelon, Kehjeng Chang, C C Liao, R S Ho, K.l. YoungAbstract:This work is designated to provide a common frame work of test chip design for technology development and Process routine Monitor, called as field-configurable test structure array (FC-TSA), which can accommodate and test the various types of test structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-test in a test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various test structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array test structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic Process to demonstrate the design feasibility. The measurements of transistor set and Process Monitor test structures are reviewed and corresponding models are discussed.
L.j. Hung - One of the best experts on this subject based on the ideXlab platform.
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field configurable test structure array fc tsa enabling design for Monitor model and manufacturability
IEEE Transactions on Semiconductor Manufacturing, 2008Co-Authors: Kelvin Y.y. Doong, L.j. Hung, T J Bordelon, Chienchih Liao, S P S Ho, Sunnys Hsieh, K.l. YoungAbstract:This paper describes a common framework of test chip design for logic technology development and routine Process Monitoring, referred to as a field-configurable test structure array (FC-TSA), which can accommodate and test various types of test structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-test within the test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various test structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40 x 20 FC-TSA has been implemented by utilizing a state-of-the-art logic Process to demonstrate design feasibility. The measurements of a set of transistor and Process Monitor test structures are reviewed and corresponding models discussed.
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field configurable test structure array fc tsa enabling design for Monitor model and manufacturability
International Conference on Microelectronic Test Structures, 2006Co-Authors: Kelvin Y.y. Doong, L.j. Hung, Sunnys Hsieh, J Bordelon, Kehjeng Chang, C C Liao, R S Ho, K.l. YoungAbstract:This work is designated to provide a common frame work of test chip design for technology development and Process routine Monitor, called as field-configurable test structure array (FC-TSA), which can accommodate and test the various types of test structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-test in a test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various test structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array test structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic Process to demonstrate the design feasibility. The measurements of transistor set and Process Monitor test structures are reviewed and corresponding models are discussed.
Jon M Schwantes - One of the best experts on this subject based on the ideXlab platform.
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proof of concept experiments of the multi isotope Process Monitor an online nondestructive near real time Monitor for spent nuclear fuel reProcessing facilities
Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment, 2012Co-Authors: Christopher R Orton, Carlos G Fraga, Richard M Christensen, Jon M SchwantesAbstract:Abstract Operators, national regulatory agencies and the IAEA will require the development of advanced technologies to efficiently control and safeguard nuclear material at increasingly large-scale nuclear recycling facilities. Ideally, the envisioned technologies would be capable of non-destructive, near real-time (NRT), autonomous Process Monitoring. This paper describes results from proof-of-principle experiments designed to test the multi-isotope Process (MIP) Monitor, a novel approach to Monitoring and safeguarding reProcessing facilities. The MIP Monitor combines the detection of intrinsic gamma ray signatures emitted from Process solutions with multivariate analysis to detect off-normal conditions in Process streams nondestructively and in NRT. Commercial spent nuclear fuel of various irradiation histories was dissolved and separated using a PUREX-based batch solvent extraction. Extractions were performed at various nitric acid concentrations to mimic both normal and off-normal industrial plant operating conditions. Principal component analysis (PCA) was applied to the simulated gamma spectra to investigate pattern variations as a function of acid concentration, burnup and cooling time. Partial least squares (PLS) regression was applied to attempt to quantify both the acid concentration and burnup of the dissolved spent fuel during the initial separation stage of recycle. The MIP Monitor demonstrated sensitivity to induced variations of acid concentration, including the distinction of ±1.3 M variation from normal Process conditions by way of PCA. Acid concentration was predicted using measurements from the organic extract and PLS resulting in predictions with
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proof of concept simulations of the multi isotope Process Monitor an online nondestructive near real time safeguards Monitor for nuclear fuel reProcessing facilities
Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment, 2011Co-Authors: Christopher R Orton, Carlos G Fraga, Richard M Christensen, Jon M SchwantesAbstract:Abstract The International Atomic Energy Agency will require the development of advanced technologies to effectively safeguard nuclear material at increasingly large-scale nuclear recycling facilities. Ideally, the envisioned technologies would be capable of nondestructive, near-real-time, autonomous Process Monitoring. This paper describes recent results from model simulations designed to test the Multi-Isotope Process (MIP) Monitor, a novel addition to a safeguards system for reProcessing facilities. The MIP Monitor combines the detection of intrinsic gamma ray signatures emitted from Process solutions with multivariate analysis to detect off-normal conditions in Process streams nondestructively and in near-real-time. Three computer models including ORIGEN-ARP, AMUSE, and SYNTH were used in series to predict spent nuclear fuel composition, estimate element partitioning during separation, and simulate spectra from product and raffinate streams using a variety of gamma detectors, respectively. Simulations were generated for fuel with various irradiation histories and under a variety of plant operating conditions. Principal component analysis was applied to the simulated gamma spectra to investigate pattern variations as a function of acid concentration, burnup, and cooling time. Hierarchical cluster analysis and partial least squares (PLS) were also used in the analysis. The MIP Monitor was found to be sensitive to induced variations of several operating parameters including distinguishing ±2.5% variation from normal Process acid concentrations. The ability of PLS to predict burnup levels from simulated spectra was also demonstrated to be within 3.5% of measured values.