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Simon Kunzli - One of the best experts on this subject based on the ideXlab platform.
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performance evaluation of network Processor Architectures combining simulation with analytical estimation
Computer Networks, 2003Co-Authors: Samarjit Chakraborty, Simon Kunzli, Lothar Thiele, Andreas Herkersdorf, Patricia M SagmeisterAbstract:The designs of most systems-on-a-chip (SoC) Architectures rely on simulation as a means for performance estimation. Such designs usually start with a parameterizable template architecture, and the design space exploration is restricted to identifying the suitable parameters for all the architectural components. However, in the case of heterogeneous SoC Architectures such as network Processors the design space exploration also involves a combinatorial aspect--which architectural components are to be chosen, how should they be interconnected, task mapping decisions--thereby increasing the design space. Moreover, in the case of network Processor Architectures there is also an associated uncertainty in terms of the application scenario and the traffic it will be required to process. As a result, simulation is no longer a feasible option for evaluating such Architectures in any automated or semi-antomated design space exploration process due to the high simulation times involved. To address this problem, in this paper we hypothesize that the design space exploration for network Processors should be separated into multiple stages, each having a different level of abstraction. Further, it would be appropriate to use analytical evaluation frameworks during the initial stages and resort to simulation techniques only when a relatively small set of potential Architectures is identified. None of the known performance evaluation methods for network Processors have been positioned from this perspective.We show that there are already suitable analytical models for network Processor performance evaluation which may be used to support our hypothesis. To this end, we choose a reference system-level model of a network Processor architecture and compare its performance evaluation results derived using a known analytical model [Thiele et al., Design space exploration of network Processor Architectures, in: Proc. 1st Workshop on Network Processors, Cambridge, MA, February 2002; Thiele et al., A framework for evaluating design tradeoffs in packet processing Architectures, in: Proc. 39th Design Automation Conference (DAC), New Orleans, USA, ACM Press, 2002] with the results derived by detailed simulation. Based on this comparison, we propose a scheme for the design space exploration of network Processor Architectures where both analytical performance evaluation techniques and simulation techniques have unique roles to play.
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chapter 4 design space exploration of network Processor Architectures
Network Processor Design, 2003Co-Authors: Samarjit Chakraborty, Matthias Gries, Simon KunzliAbstract:It is noted that network Processors (NPs) generally consist of multiple processing units such as CPU cores, microengines, and dedicated hardware for computing-intensive tasks, memory units, caches, interconnections, and I/O interfaces. Following a system-on-a-chip (SoC) design method, these resources are then put on a single chip and they must interoperate in order to perform packet processing tasks at line speed. The process of determining the optimal hardware and software architecture for such Processors includes issues involving resource allocation and partitioning. The chapter presents a framework for the design space exploration of embedded systems. It is observed that the architecture exploration and evaluation of network Processors involve many tradeoffs and a complex interplay between hardware and software. The chapter focuses on high level of abstraction, where the goal is to quickly identify interesting Architectures that can be further evaluated by taking lower-level details into account. Task models, task scheduling, operating system issues, and packet Processor Architectures collectively play a role in different phases of the design space exploration of packet Processor devices.
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a framework for evaluating design tradeoffs in packet processing Architectures
Design Automation Conference, 2002Co-Authors: Lothar Thiele, Matthias Gries, Samarjit Chakraborty, Simon KunzliAbstract:We present an analytical method to evaluate embedded network packet Processor Architectures, and to explore their design space. Our approach is in contrast to those based on simulation, which tend to be infeasible when the design space is very large. We illustrate the feasibility of our method using a detailed case study.
Shih Chii Liu - One of the best experts on this subject based on the ideXlab platform.
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Memory and Information Processing in Neuromorphic Systems
Proceedings of the IEEE, 2015Co-Authors: Giacomo Indiveri, Shih Chii LiuAbstract:A striking difference between brain-inspired neuromorphic Processors and current von Neumann Processors Architectures is the way in which memory and processing is organized. As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital Processor, neuromorphic engineers and scientists can complement this need by building Processor Architectures where memory is distributed with the processing. In this paper we present a survey of brain-inspired Processor Architectures that support models of cortical networks and deep neural networks. These Architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness of behaviors seen in biological systems.
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memory and information processing in neuromorphic systems in neuromorphic approaches memories are distributed this paper reviews the Architectures of cortical and deep neural networks inspired by the brain and raises the issues that need to be tackled for these neuromorphic approaches to reach toward full biological richness
2015Co-Authors: Giacomo Indiveri, Shih Chii LiuAbstract:A striking difference between brain-inspired neu- romorphic Processors and current von Neumann Processor Architectures is the way in which memory and processing is organized. As information and communication technologies continue to address the need for increased computational power through the increase of cores within a digital Processor, neuromorphic engineers and scientists can complement this need by building Processor Architectures where memory is distributed with the processing. In this paper, we present a survey of brain-inspired Processor Architectures that support models of cortical networks and deep neural networks. These Architectures range from serial clocked implementations of multineuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital sys- tems which implement more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different ap- proaches being pursued and present the challenges that need to be addressed for building artificial neural processing sys- tems that can display the richness of behaviors seen in biolo- gical systems.
Tamer M Ozsu - One of the best experts on this subject based on the ideXlab platform.
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main memory hash joins on modern Processor Architectures
IEEE Transactions on Knowledge and Data Engineering, 2015Co-Authors: Cagri Balkesen, Jens Teubner, Gustavo Alonso, Tamer M OzsuAbstract:Existing main-memory hash join algorithms for multi-core can be classified into two camps. Hardware-oblivious hash join variants do not depend on hardware-specific parameters. Rather, they consider qualitative characteristics of modern hardware and are expected to achieve good performance on any technologically similar platform. The assumption behind these algorithms is that hardware is now good enough at hiding its own limitations—through automatic hardware prefetching, out-of-order execution, or simultaneous multi-threading (SMT)—to make hardware-oblivious algorithms competitive without the overhead of carefully tuning to the underlying hardware. Hardware-conscious implementations, such as (parallel) radix join , aim to maximally exploit a given architecture by tuning the algorithm parameters (e.g., hash table sizes) to the particular features of the architecture. The assumption here is that explicit parameter tuning yields enough performance advantages to warrant the effort required. This paper compares the two approaches under a wide range of workloads (relative table sizes, tuple sizes, effects of sorted data, etc.) and configuration parameters (VM page sizes, number of threads, number of cores, SMT, SIMD, prefetching, etc.). The results show that hardware-conscious algorithms generally outperform hardware-oblivious ones. However, on specific workloads and special Architectures with aggressive simultaneous multi-threading, hardware-oblivious algorithms are competitive. The main conclusion of the paper is that, in existing multi-core Architectures, it is still important to carefully tailor algorithms to the underlying hardware to get the necessary performance. But Processor developments may require to revisit this conclusion in the future.
Vassilis J Tsotras - One of the best experts on this subject based on the ideXlab platform.
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fpga based multithreading for in memory hash joins
Conference on Innovative Data Systems Research, 2015Co-Authors: Robert J Halstead, Ildar Absalyamov, Walid Najjar, Vassilis J TsotrasAbstract:Large relational databases often rely on fast join implementations for good performance. Recent paradigm shifts in Processor Architectures has reinvigorated research into how the join operation can be implemented. The FPGA community has also been developing new Architectures with the potential to push performance even further. Hashing is a common method used to implement joins, but its poor spatial locality can hinder performance on Processor Architectures. Multithreaded Architectures can better cope with poor spatial locality by masking memory/cache latencies with many outstanding requests. In this paper we present the first end-to-end in-memory FPGA hash join implementation. The FGPA uses massive multithreading during the build and probe phases to mask long memory delays, while it concurrently manages hundreds of thread states locally. Throughput results show a speedup between 2x and 3.4x over the best multi-core approaches with comparable memory bandwidths on uniform and skewed datasets; however, this advantage diminishes for extremely skewed datasets. Results using the FPGA’s full 76.8 GB/s of bandwidth show throughput up to 1.6 billion tuples per second for uniform and skewed datasets.
Samarjit Chakraborty - One of the best experts on this subject based on the ideXlab platform.
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performance evaluation of network Processor Architectures combining simulation with analytical estimation
Computer Networks, 2003Co-Authors: Samarjit Chakraborty, Simon Kunzli, Lothar Thiele, Andreas Herkersdorf, Patricia M SagmeisterAbstract:The designs of most systems-on-a-chip (SoC) Architectures rely on simulation as a means for performance estimation. Such designs usually start with a parameterizable template architecture, and the design space exploration is restricted to identifying the suitable parameters for all the architectural components. However, in the case of heterogeneous SoC Architectures such as network Processors the design space exploration also involves a combinatorial aspect--which architectural components are to be chosen, how should they be interconnected, task mapping decisions--thereby increasing the design space. Moreover, in the case of network Processor Architectures there is also an associated uncertainty in terms of the application scenario and the traffic it will be required to process. As a result, simulation is no longer a feasible option for evaluating such Architectures in any automated or semi-antomated design space exploration process due to the high simulation times involved. To address this problem, in this paper we hypothesize that the design space exploration for network Processors should be separated into multiple stages, each having a different level of abstraction. Further, it would be appropriate to use analytical evaluation frameworks during the initial stages and resort to simulation techniques only when a relatively small set of potential Architectures is identified. None of the known performance evaluation methods for network Processors have been positioned from this perspective.We show that there are already suitable analytical models for network Processor performance evaluation which may be used to support our hypothesis. To this end, we choose a reference system-level model of a network Processor architecture and compare its performance evaluation results derived using a known analytical model [Thiele et al., Design space exploration of network Processor Architectures, in: Proc. 1st Workshop on Network Processors, Cambridge, MA, February 2002; Thiele et al., A framework for evaluating design tradeoffs in packet processing Architectures, in: Proc. 39th Design Automation Conference (DAC), New Orleans, USA, ACM Press, 2002] with the results derived by detailed simulation. Based on this comparison, we propose a scheme for the design space exploration of network Processor Architectures where both analytical performance evaluation techniques and simulation techniques have unique roles to play.
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chapter 4 design space exploration of network Processor Architectures
Network Processor Design, 2003Co-Authors: Samarjit Chakraborty, Matthias Gries, Simon KunzliAbstract:It is noted that network Processors (NPs) generally consist of multiple processing units such as CPU cores, microengines, and dedicated hardware for computing-intensive tasks, memory units, caches, interconnections, and I/O interfaces. Following a system-on-a-chip (SoC) design method, these resources are then put on a single chip and they must interoperate in order to perform packet processing tasks at line speed. The process of determining the optimal hardware and software architecture for such Processors includes issues involving resource allocation and partitioning. The chapter presents a framework for the design space exploration of embedded systems. It is observed that the architecture exploration and evaluation of network Processors involve many tradeoffs and a complex interplay between hardware and software. The chapter focuses on high level of abstraction, where the goal is to quickly identify interesting Architectures that can be further evaluated by taking lower-level details into account. Task models, task scheduling, operating system issues, and packet Processor Architectures collectively play a role in different phases of the design space exploration of packet Processor devices.
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a framework for evaluating design tradeoffs in packet processing Architectures
Design Automation Conference, 2002Co-Authors: Lothar Thiele, Matthias Gries, Samarjit Chakraborty, Simon KunzliAbstract:We present an analytical method to evaluate embedded network packet Processor Architectures, and to explore their design space. Our approach is in contrast to those based on simulation, which tend to be infeasible when the design space is very large. We illustrate the feasibility of our method using a detailed case study.