The Experts below are selected from a list of 19911 Experts worldwide ranked by ideXlab platform

Qingsong Wei - One of the best experts on this subject based on the ideXlab platform.

Mohammad Shihabul Haque - One of the best experts on this subject based on the ideXlab platform.

  • ISORC - A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems
    2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC), 2018
    Co-Authors: Mohammad Shihabul Haque, Sriram Vasudevan, Alamuri Sriram Nihar, Arvind Easwaran, Akash Kumar
    Abstract:

    Quality of control is a critical concern in Cyber-Physical Systems (CPS) which are comprised of multiple intercommunicating control applications. Due to complex timing behaviour of these systems, poor quality of control can lead to catastrophe. Recent studies showed that, conflict miss increment in the Processor Cache memory shared by concurrently running control applications can degrade control quality in CPS significantly. Increasing Cache associativity can help to reduce conflict misses. However, the existing reconfigurable Cache architectures that allow runtime modification of Cache associativity are not capable to guaranty a newly chosen associativity's suitability for the forthcoming control quality requirement. Moreover, they have timing and energy related overheads. In this regard, this paper presents a novel, self-reconfiguring Cache memory architecture "SeReMo". When conflict misses increase significantly, SeReMo reconfigures its associativity to better suit the current as well as future control quality demand. To trigger reconfiguration, a low overhead, non-strictly inclusive Cache hierarchy-specific approach is used. Configurations with different associativity are generated using modules made of 4 Cache lines and 7 special bits. Special replacement policy and indexing scheme are used to suit modular reconfiguration. SPEC CPU 2006 benchmark trace-driven simulation reveals that SeReMo reduces average number of conflict misses per line to 1/12951 of the state-of-the-art reconfigurable Cache architecture at maximum (to 1/830 on average). As a result, execution time and energy consumption reduce by 48 hours at maximum (by 2/3 on average) and by 2907 Joules at maximum (86% on average) respectively.

  • ASP-DAC - Accelerating non-volatile/hybrid Processor Cache design space exploration for application specific embedded systems
    The 20th Asia and South Pacific Design Automation Conference, 2015
    Co-Authors: Mohammad Shihabul Haque, Akash Kumar, Qingsong Wei
    Abstract:

    In this article, we propose a technique to accelerate non-volatile/hybrid of volatile and non-volatile Processor Cache design space exploration for application specific embedded systems. Utilizing a novel Cache behavior modeling equation and a new accurate Cache miss prediction mechanism, our proposed technique can accelerate NVM/hybrid FIFO Processor Cache design space exploration for SPEC CPU 2000 applications up to 249 times compared to the conventional approach.

Francisco J Cazorla - One of the best experts on this subject based on the ideXlab platform.

  • random modulo a new Processor Cache design for real time critical systems
    Design Automation Conference, 2016
    Co-Authors: Carles Hernandez, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J Cazorla
    Abstract:

    Cache memories have a huge impact on software's worst-case execution time (WCET). While enabling the seamless use of Caches is key to provide the increasing levels of (guaranteed) performance required by automotive software, Caches complicate timing analysis. In the context of Measurement-Based Probabilistic Timing Analysis (MBPTA) -- a promising technique to ease timing analyis of complex hardware -- we propose Random Modulo (RM), a new Cache design that provides the probabilistic behavior required by MBPTA and with the following advantages over existing MBPTA-compliant Cache designs: (i) an outstanding reduction in WCET estimates, (ii) lower latency and area overhead, and (iii) competitive average performance w.r.t conventional Caches.

  • DAC - Random modulo: a new Processor Cache design for real-time critical systems
    Proceedings of the 53rd Annual Design Automation Conference on - DAC '16, 2016
    Co-Authors: Carles Hernandez, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J Cazorla
    Abstract:

    Cache memories have a huge impact on software's worst-case execution time (WCET). While enabling the seamless use of Caches is key to provide the increasing levels of (guaranteed) performance required by automotive software, Caches complicate timing analysis. In the context of Measurement-Based Probabilistic Timing Analysis (MBPTA) -- a promising technique to ease timing analyis of complex hardware -- we propose Random Modulo (RM), a new Cache design that provides the probabilistic behavior required by MBPTA and with the following advantages over existing MBPTA-compliant Cache designs: (i) an outstanding reduction in WCET estimates, (ii) lower latency and area overhead, and (iii) competitive average performance w.r.t conventional Caches.

Stephan Thesing - One of the best experts on this subject based on the ideXlab platform.

  • Cache Aware Pre-Runtime Scheduling
    Real-Time Systems, 1999
    Co-Authors: Daniel Kästner, Stephan Thesing
    Abstract:

    We present a novel pre-runtime scheduling method for uniProcessors which precisely takes the effects of task switching on the Processor Cache into consideration. Tasks are modelled as a sequence of non preemptable segments with precedence constraints. The Cache behavior of each task segment is statically determined by abstract interpretation. For the sake of efficiency, the scheduling algorithm uses a heuristically guided search strategy. Each time a new task segment is added to a partial schedule, its worst case execution time is calculated based on the Cache state at the end of the preceding partial schedule.

  • Cache sensitive pre-runtime scheduling
    Lecture Notes in Computer Science, 1998
    Co-Authors: Daniel Kästner, Stephan Thesing
    Abstract:

    We present a novel pre-runtime scheduling method for uniProcessors which precisely incorporates the effects of task switching on the Processor Cache into its decisions. Tasks are modelled as a sequence of non preemtable segments with precedence constraints. The Cache behavior of each task segment is statically determined by abstract interpretation. For the sake of efficiency, the scheduling algorithm uses a heuristically guided search strategy. Each time a new task segment is added to a partial schedule, its worst case execution time is calculated based on the Cache state at the end of the preceding partial schedule.

Michael Parker - One of the best experts on this subject based on the ideXlab platform.

  • The Impulse memory controller
    IEEE Transactions on Computers, 2001
    Co-Authors: Lixin Zhang, Binu K. Mathew, Lambert Schaelicke, John B. Carter, Wilson C. Hsieh, Michael Parker, Zhen Fang, Sally A. Mckee
    Abstract:

    Impulse is a memory system architecture that adds an optional level of address indirection at the memory controller. Applications can use this level of indirection to remap their data structures in memory. As a result, they can control how their data is accessed and Cached, which can improve Cache and bus utilization. The Impulse design does not require any modification to Processor, Cache, or bus designs since all the functionality resides at the memory controller. As a result, Impulse can be adopted in conventional systems without major system changes. We describe the design of the Impulse architecture and how an Impulse memory system can be used in a variety of ways to improve the performance of memory-bound applications. Impulse can be used to dynamically create superpages cheaply, to dynamically recolor physical pages, to perform strided fetches, and to perform gathers and scatters through indirection vectors. Our performance results demonstrate the effectiveness of these optimizations in a variety of scenarios. Using Impulse can speed up a range of applications from 20 percent to over a factor of 5. Alternatively, Impulse can be used by the OS for dynamic superpage creation; the best policy for creating superpages using Impulse outperforms previously known superpage creation policies.

  • impulse building a smarter memory controller
    High-Performance Computer Architecture, 1999
    Co-Authors: John B. Carter, Leigh Stoller, Erik Brunvand, Al Davis, R Kuramkote, M Swanson, Wilson C. Hsieh, Lixin Zhang, Michael Parker, Lambert Schaelicke
    Abstract:

    Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and Cached, improving their Cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system can be used to improve the performance of memory-bound programs. For the NAS conjugate gradient benchmark, Impulse improves performance by 67%. Because it requires no modification to Processor, Cache, or bus designs, Impulse can be adopted in conventional systems. In addition to scientific applications, we expect that Impulse will benefit regularly strided memory-bound applications of commercial importance, such as database and multimedia programs.

  • HPCA - Impulse: building a smarter memory controller
    Proceedings Fifth International Symposium on High-Performance Computer Architecture, 1999
    Co-Authors: John B. Carter, Leigh Stoller, Erik Brunvand, Al Davis, R Kuramkote, M Swanson, Wilson C. Hsieh, Lixin Zhang, Michael Parker
    Abstract:

    Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and Cached, improving their Cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system can be used to improve the performance of memory-bound programs. For the NAS conjugate gradient benchmark, Impulse improves performance by 67%. Because it requires no modification to Processor, Cache, or bus designs, Impulse can be adopted in conventional systems. In addition to scientific applications, we expect that Impulse will benefit regularly strided memory-bound applications of commercial importance, such as database and multimedia programs.