The Experts below are selected from a list of 11994 Experts worldwide ranked by ideXlab platform
Abhik Roychoudhury - One of the best experts on this subject based on the ideXlab platform.
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Memory model sensitive bytecode verification
Formal Methods in System Design, 2007Co-Authors: Thuan Quang Huynh, Abhik RoychoudhuryAbstract:Modern concurrent Programming languages like C# and Java have a Programming language level memory model, which captures the set of all allowed behaviors of Programs on any implementation platform—uni- or multi-processor. Such a memory model is typically weaker than Sequential Consistency and allows reordering of operations within a Program Thread. Therefore, Programs verified correct by assuming Sequential Consistency (that is, each Thread proceeds in Program order) may not behave correctly on certain platforms! One solution to this problem is to develop Program checkers which are memory model sensitive. In this paper, we develop a bytecode level invariant checker for the Programming language C#. Our checker identifies Program states which are reached only because the C# memory model is more relaxed than Sequential Consistency. It employs partial order reduction strategies to speed up the search. These strategies are different from standard partial order reduction methods since our search also considers execution traces containing bytecode re-orderings. Furthermore, our checker identifies (a) operation re-orderings which cause undesirable states to be reached, and (b) simple Program modifications—by inserting memory barrier operations—which prevent such undesirable re-orderings.
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FM - A memory model sensitive checker for c
FM 2006: Formal Methods, 2006Co-Authors: Thuan Quang Huynh, Abhik RoychoudhuryAbstract:Modern concurrent Programming languages like Java and C# have a Programming language level memory model; it captures the set of all allowed behaviors of Programs on any implementation platform — uni- or multi-processor. Such a memory model is typically weaker than Sequential Consistency and allows reordering of operations within a Program Thread. Therefore, Programs verified correct by assuming Sequential Consistency (that is, each Thread proceeds in Program order) may not behave correctly on certain platforms! The solution to this problem is to develop Program checkers which are memory model sensitive. In this paper, we develop such an invariant checker for the Programming language C#. Our checker identifies Program states which are reached only because the C# memory model is more relaxed than Sequential Consistency. Furthermore, our checker identifies (a) operation reorderings which cause such undesirable states to be reached, and (b) simple Program modifications — by inserting memory barrier operations — which prevent such undesirable reorderings.
Thuan Quang Huynh - One of the best experts on this subject based on the ideXlab platform.
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Memory model sensitive bytecode verification
Formal Methods in System Design, 2007Co-Authors: Thuan Quang Huynh, Abhik RoychoudhuryAbstract:Modern concurrent Programming languages like C# and Java have a Programming language level memory model, which captures the set of all allowed behaviors of Programs on any implementation platform—uni- or multi-processor. Such a memory model is typically weaker than Sequential Consistency and allows reordering of operations within a Program Thread. Therefore, Programs verified correct by assuming Sequential Consistency (that is, each Thread proceeds in Program order) may not behave correctly on certain platforms! One solution to this problem is to develop Program checkers which are memory model sensitive. In this paper, we develop a bytecode level invariant checker for the Programming language C#. Our checker identifies Program states which are reached only because the C# memory model is more relaxed than Sequential Consistency. It employs partial order reduction strategies to speed up the search. These strategies are different from standard partial order reduction methods since our search also considers execution traces containing bytecode re-orderings. Furthermore, our checker identifies (a) operation re-orderings which cause undesirable states to be reached, and (b) simple Program modifications—by inserting memory barrier operations—which prevent such undesirable re-orderings.
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FM - A memory model sensitive checker for c
FM 2006: Formal Methods, 2006Co-Authors: Thuan Quang Huynh, Abhik RoychoudhuryAbstract:Modern concurrent Programming languages like Java and C# have a Programming language level memory model; it captures the set of all allowed behaviors of Programs on any implementation platform — uni- or multi-processor. Such a memory model is typically weaker than Sequential Consistency and allows reordering of operations within a Program Thread. Therefore, Programs verified correct by assuming Sequential Consistency (that is, each Thread proceeds in Program order) may not behave correctly on certain platforms! The solution to this problem is to develop Program checkers which are memory model sensitive. In this paper, we develop such an invariant checker for the Programming language C#. Our checker identifies Program states which are reached only because the C# memory model is more relaxed than Sequential Consistency. Furthermore, our checker identifies (a) operation reorderings which cause such undesirable states to be reached, and (b) simple Program modifications — by inserting memory barrier operations — which prevent such undesirable reorderings.
Bruce R Childers - One of the best experts on this subject based on the ideXlab platform.
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using utility prediction models to dynamically choose Program Thread counts
International Symposium on Performance Analysis of Systems and Software, 2012Co-Authors: Ryan W Moore, Bruce R ChildersAbstract:MultiThreaded applications can simultaneously execute on a chip multiprocessor computer, starting and stopping without warning or pattern. The behavior of each Program can be different, interacting in unexpected ways, including causing competition for CPU cycles, which harms performance.
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ISPASS - Using utility prediction models to dynamically choose Program Thread counts
2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012Co-Authors: Ryan W Moore, Bruce R ChildersAbstract:MultiThreaded applications can simultaneously execute on a chip multiprocessor computer, starting and stopping without warning or pattern. The behavior of each Program can be different, interacting in unexpected ways, including causing competition for CPU cycles, which harms performance.
Ryan W Moore - One of the best experts on this subject based on the ideXlab platform.
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using utility prediction models to dynamically choose Program Thread counts
International Symposium on Performance Analysis of Systems and Software, 2012Co-Authors: Ryan W Moore, Bruce R ChildersAbstract:MultiThreaded applications can simultaneously execute on a chip multiprocessor computer, starting and stopping without warning or pattern. The behavior of each Program can be different, interacting in unexpected ways, including causing competition for CPU cycles, which harms performance.
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ISPASS - Using utility prediction models to dynamically choose Program Thread counts
2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012Co-Authors: Ryan W Moore, Bruce R ChildersAbstract:MultiThreaded applications can simultaneously execute on a chip multiprocessor computer, starting and stopping without warning or pattern. The behavior of each Program can be different, interacting in unexpected ways, including causing competition for CPU cycles, which harms performance.
Philip A. Wilsey - One of the best experts on this subject based on the ideXlab platform.
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ICPP Workshops - Pre-computing Function Results in Multi-Core and Many-Core Processors
2011 40th International Conference on Parallel Processing Workshops, 2011Co-Authors: Edward C. Herrmann, Prudhvi Janga, Philip A. WilseyAbstract:In recent years, the number of hardware supported Threads in desktop processors has increased dramatically. All but the very lowest cost net books and embedded processors now have at least dual cores and soon systems supporting upwards of 8 to 16 hardware Threads are likely to be commonplace. Unfortunately, it will be difficult to take full advantage of the parallelism emerging processors will be able to provide. To help address this issue, we are investigating mechanisms to pre-compute function results in separate Threads running concurrently with the main Program Thread. The concurrent Threads are forked automatically and without Program modification. A critical component for the success of this idea is an ability to build a background Thread that can pre-compute usable results in some effective manner. For some support functions (dynamic memory) exact arguments predictions for the function pre-computation are not necessary, for others (trigonometric functions) they are. In work with dynamic memory, we are able to pre-compute memory blocks and show modest speedup: saving approximately 25\% of the dynamic memory costs. In studies with predicting argument values to trigonometric functions, we show that learning algorithms are able to successfully predict the next argument values approximately 44\% of the time.
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CISIS - Threaded Dynamic Memory Management in Many-Core Processors
2010 International Conference on Complex Intelligent and Software Intensive Systems, 2010Co-Authors: Edward C. Herrmann, Philip A. WilseyAbstract:Current trends in desktop processor design have been toward many-core solutions with increased parallelism. As the number of supported Threads grows in these processors, it may prove difficult to exploit them on the commodity desktop. This paper presents a study that explores the spawning of the dynamic memory management activities into a separately executing Thread that runs concurrently with the main Program Thread. Our approach works without requiring modifications to the original source Program by redefining the dynamic link path to capture malloc and free calls in a Threading dynamic memory management library. The routines of this library are setup so that the initial call to malloc triggers the creation of a Thread for dynamic memory management; successive calls to malloc and free will trigger coordination with this Thread for dynamic memory management activities. Our preliminary studies show that we can transparently redefine the dynamic memory management activities and we have successfully done so for numerous test Programs including most of the SPEC CPU2006 benchmarks, Firefox, and other unix utilities. The results of our experiments show that it is possible to achieve 2-3% performance gains in the three most memory-intensive SPEC CPU2006 benchmarks without requiring recompilation of the benchmark source code. We were also able to achieve a 3-4% speedup when using our library with the gcc and llvm compilers.