The Experts below are selected from a list of 4377 Experts worldwide ranked by ideXlab platform
Prashant S Chauhan - One of the best experts on this subject based on the ideXlab platform.
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a parallel Progressive Refinement image rendering algorithm on a scalable multithreaded vlsi processor array
International Conference on Parallel Processing, 1993Co-Authors: S K Nandy, Ranjani Narayan, V Visvanathan, P Sadayappan, Prashant S ChauhanAbstract:In this paper we develop a multithreaded VLSI processor linear array architecture to render complex environments based on the radiosity approach. The processing elements are identical and multithreaded. They work in Single Program Multiple Data (SPMD) mode. A new algorithm to do the radiosity computations based on the Progressive Refinement approach[2] is proposed. Simulation results indicate that the architecture is latency tolerant and scalable. It is shown that a linear array of 128 uni-threaded processing elements sustains a throughput close to 0.4 million patches/sec.
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ICPP (3) - A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array
1993 International Conference on Parallel Processing - ICPP'93 Vol3, 1993Co-Authors: S K Nandy, Ranjani Narayan, V Visvanathan, P Sadayappan, Prashant S ChauhanAbstract:In this paper we develop a multithreaded VLSI processor linear array architecture to render complex environments based on the radiosity approach. The processing elements are identical and multithreaded. They work in Single Program Multiple Data (SPMD) mode. A new algorithm to do the radiosity computations based on the Progressive Refinement approach[2] is proposed. Simulation results indicate that the architecture is latency tolerant and scalable. It is shown that a linear array of 128 uni-threaded processing elements sustains a throughput close to 0.4 million patches/sec.
Christian Masson - One of the best experts on this subject based on the ideXlab platform.
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Zephyr: a Static Timing Analyzer integrated in a trans-hierarchical Refinement design flow
2006Co-Authors: Christophe Alexandre, Marek Sroka, Hugo Clement, Christian MassonAbstract:The evolution of silicon technologies has fundamentally changed the physical design EDA flow, which now has to go through a Progressive Refinement process where interconnections evolve seamlessly from logic to final detailed routing. Furthermore the level of integration reached makes mandatory the use of hierarchical enabled design methodologies. In this paper, we present Zephyr: an Elmore Delay Static Timing Analysis engine tightly integrated in the open academic Coriolis EDA physical design platform on which tools act as algorithmic engines operating on an integrated C++ database around which they consistently interact and collaborate. Coriolis provides high level C++ and Python APIs and a unified and consistent hierarchical VLSI data model through all the design steps from logic down to final layout. We discuss here more specifically the integration issues and concepts used to support timing analysis through the Progressive Refinement of hierarchical designs.
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PATMOS - Zephyr: a static timing analyzer integrated in a trans-hierarchical Refinement design flow
Lecture Notes in Computer Science, 2006Co-Authors: Christophe Alexandre, Marek Sroka, Hugo Clement, Christian MassonAbstract:The evolution of silicon technologies has fundamentally changed the physical design EDA flow, which now has to go through a Progressive Refinement process where interconnections evolve seamlessly from logic to final detailed routing. Furthermore the level of integration reached makes mandatory the use of hierarchical enabled design methodologies. In this paper, we present Zephyr: an Elmore Delay Static Timing Analysis engine tightly integrated in the open academic Coriolis EDA physical design platform on which tools act as algorithmic engines operating on an integrated C++ database around which they consistently interact and collaborate. Coriolis provides high level C++ and Python APIs and a unified and consistent hierarchical VLSI data model through all the design steps from logic down to final layout. We discuss here more specifically the integration issues and concepts used to support timing analysis through the Progressive Refinement of hierarchical designs.
S K Nandy - One of the best experts on this subject based on the ideXlab platform.
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a parallel Progressive Refinement image rendering algorithm on a scalable multithreaded vlsi processor array
International Conference on Parallel Processing, 1993Co-Authors: S K Nandy, Ranjani Narayan, V Visvanathan, P Sadayappan, Prashant S ChauhanAbstract:In this paper we develop a multithreaded VLSI processor linear array architecture to render complex environments based on the radiosity approach. The processing elements are identical and multithreaded. They work in Single Program Multiple Data (SPMD) mode. A new algorithm to do the radiosity computations based on the Progressive Refinement approach[2] is proposed. Simulation results indicate that the architecture is latency tolerant and scalable. It is shown that a linear array of 128 uni-threaded processing elements sustains a throughput close to 0.4 million patches/sec.
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ICPP (3) - A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array
1993 International Conference on Parallel Processing - ICPP'93 Vol3, 1993Co-Authors: S K Nandy, Ranjani Narayan, V Visvanathan, P Sadayappan, Prashant S ChauhanAbstract:In this paper we develop a multithreaded VLSI processor linear array architecture to render complex environments based on the radiosity approach. The processing elements are identical and multithreaded. They work in Single Program Multiple Data (SPMD) mode. A new algorithm to do the radiosity computations based on the Progressive Refinement approach[2] is proposed. Simulation results indicate that the architecture is latency tolerant and scalable. It is shown that a linear array of 128 uni-threaded processing elements sustains a throughput close to 0.4 million patches/sec.
Christophe Alexandre - One of the best experts on this subject based on the ideXlab platform.
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Zephyr: a Static Timing Analyzer integrated in a trans-hierarchical Refinement design flow
2006Co-Authors: Christophe Alexandre, Marek Sroka, Hugo Clement, Christian MassonAbstract:The evolution of silicon technologies has fundamentally changed the physical design EDA flow, which now has to go through a Progressive Refinement process where interconnections evolve seamlessly from logic to final detailed routing. Furthermore the level of integration reached makes mandatory the use of hierarchical enabled design methodologies. In this paper, we present Zephyr: an Elmore Delay Static Timing Analysis engine tightly integrated in the open academic Coriolis EDA physical design platform on which tools act as algorithmic engines operating on an integrated C++ database around which they consistently interact and collaborate. Coriolis provides high level C++ and Python APIs and a unified and consistent hierarchical VLSI data model through all the design steps from logic down to final layout. We discuss here more specifically the integration issues and concepts used to support timing analysis through the Progressive Refinement of hierarchical designs.
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PATMOS - Zephyr: a static timing analyzer integrated in a trans-hierarchical Refinement design flow
Lecture Notes in Computer Science, 2006Co-Authors: Christophe Alexandre, Marek Sroka, Hugo Clement, Christian MassonAbstract:The evolution of silicon technologies has fundamentally changed the physical design EDA flow, which now has to go through a Progressive Refinement process where interconnections evolve seamlessly from logic to final detailed routing. Furthermore the level of integration reached makes mandatory the use of hierarchical enabled design methodologies. In this paper, we present Zephyr: an Elmore Delay Static Timing Analysis engine tightly integrated in the open academic Coriolis EDA physical design platform on which tools act as algorithmic engines operating on an integrated C++ database around which they consistently interact and collaborate. Coriolis provides high level C++ and Python APIs and a unified and consistent hierarchical VLSI data model through all the design steps from logic down to final layout. We discuss here more specifically the integration issues and concepts used to support timing analysis through the Progressive Refinement of hierarchical designs.
Pat Hanrahan - One of the best experts on this subject based on the ideXlab platform.
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hierarchical splatting a Progressive Refinement algorithm for volume rendering
International Conference on Computer Graphics and Interactive Techniques, 1991Co-Authors: David Laur, Pat HanrahanAbstract:This paper presents a Progressive Refinement algorithm for volume rendering which uses a pyramidal volume representation. Besides storing average values, the pyramid stores estimated error, so an octtree can be fit to the pyramid given a user-supplied precision. This octtree is then drawn using a set of splats, or footprints, each scaled to match the size of the projection of a cell. The splats themselves are approximated with RGBA Gouraud-shaded polygons, so that they can be drawn efficiently on modern graphics workstations. The result is a real-time rendering algorithm suitable for interactive applications.
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SIGGRAPH - Hierarchical splatting: a Progressive Refinement algorithm for volume rendering
Proceedings of the 18th annual conference on Computer graphics and interactive techniques - SIGGRAPH '91, 1991Co-Authors: David Laur, Pat HanrahanAbstract:This paper presents a Progressive Refinement algorithm for volume rendering which uses a pyramidal volume representation. Besides storing average values, the pyramid stores estimated error, so an octtree can be fit to the pyramid given a user-supplied precision. This octtree is then drawn using a set of splats, or footprints, each scaled to match the size of the projection of a cell. The splats themselves are approximated with RGBA Gouraud-shaded polygons, so that they can be drawn efficiently on modern graphics workstations. The result is a real-time rendering algorithm suitable for interactive applications.
