The Experts below are selected from a list of 153 Experts worldwide ranked by ideXlab platform
René Schüffny - One of the best experts on this subject based on the ideXlab platform.
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ISCAS - A Pulse Communication flow ready for accelerated neuromorphic experiments
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014Co-Authors: V. Thanasoulis, Bernhard Vogginger, Johannes Partzsch, René SchüffnyAbstract:Large-scale neuromorphic systems demand a sophisticated Communication infrastructure to support several functionalities like configuration of neuron-and-synapse blocks, Pulse stimulation, routing and tracing of the neural activity. This infrastructure is usually implemented around custom-designed FPGA systems. Performance requirements for these systems significantly increase when emulating the biological counterpart at an accelerated timescale. In this paper we characterize the capability of such a system to provide accurate long-term stimulation for emulated spiking networks and tracing of their activity. The design has a capacity of 1 billion timestamped events for both stimulation and tracing with a time resolution up to 48 ns. We characterize the Communication flow in terms of throughput, transmission delay, packet loss and jitter. The results show that the implementation meets the needs of learning experiments, which is an important issue for state-of-the-art neuromorphic systems.
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VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality.
Frontiers in neuroscience, 2011Co-Authors: Stefan Scholze, Bernhard Vogginger, Johannes Partzsch, Stefan Schiefer, Stephan Hartmann, Christian Mayr, Stephan Henker, Sebastian Hoppner, Holger Eisenreich, René SchüffnyAbstract:State-of-the-art large scale neuromorphic systems require sophisticated spike event Communication between units of the neural network. We present a high-speed Communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic Communication ICs in an FPGA-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behaviour of neuromorphic benchmarks. The specialized, dedicated AER Communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based Pulse channel, which transmits configuration data at the full bandwidth otherwise used for Pulse transmission. The overall so-called Pulse Communication subgroup (ICs and FPGA) delivers a factor 25-50 more event transmission rate than other current neuromorphic Communication infrastructures.
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ISCAS - Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011Co-Authors: Stefan Schiefer, Johannes Partzsch, Stephan Hartmann, Stefan Scholze, Christian Mayr, Stephan Henker, René SchüffnyAbstract:Traditionally, the Communication in neuromorphic VLSI systems has been done via parallel asynchronous transmission of Address-Event-Representations (AER) of neuron Pulses. Recently, there has been a move towards greater event transmission speed via a serialization of the AER protocols. We give a live demonstration of a packet based synchronous serial AER infrastructure presented in a recent paper [1], which handles the complete off-wafer Communication and configuration for a newly developed waferscale neuromorphic system [2]1, operating at a factor of 104 faster than biological real-time. Pulse packets are routed from the host PC via Gbit Ethernet to an FPGA board (see Fig. 1), which forwards them to 4 purpose designed Digital Network ASICs (DNCs) on the same board. The DNCs buffer and sort the Pulses, implementing 32 2GBit/s Low Voltage Differential Signaling (LVDS) interfaces to the neuromorphic circuits on the wafer. Pulse Communication to other wafers is done via an FPGA-FPGA Communication using 10Gbit/s Aurora links.
Jawad A. Salehi - One of the best experts on this subject based on the ideXlab platform.
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Statistical Modeling and Performance Characterization of Ultrashort Light Pulse Communication System Using Power-Cubic Optical Nonlinear Preprocessor
IEEE Transactions on Communications, 2015Co-Authors: Ranjbar Zefreh, Jawad A. SalehiAbstract:In this paper, we present an analytical approach in obtaining the probability density function (pdf) of the random decision variable $\boldsymbol{Y} $ , which is formed at the output of the power-cubic all-optical nonlinear preprocessor followed by the photodetector, with applications in ultrafast optical time-division multiplexing and optical code-division multiple-access systems. Our approach can be used to accurately evaluate the performance of ultrafast Pulse detection in the presence of Gaussian noise. Through rigorous Monte Carlo simulation, the accuracy of the widely used Gaussian approximation of decision variable $\boldsymbol{Y} $ is refuted. However, in this paper, we show that the so-called log-Pearson type-3 (LP3) pdf is an excellent representation for the decision variable $\boldsymbol{Y} $ . Three distinguishable parameters of the LP3 pdf are obtained through an analytical derivation of three moments of the decision variable $\boldsymbol{Y} $ . Furthermore, toward a more realistic model, in addition to amplified spontaneous emission Gaussian noise, the effects of shot and thermal noises are also included. Finally, using the presented analytical approach, it is shown that the power-cubic preprocessor outperforms its quadratic counterparts, i.e., second-harmonic-generation and two-photon-absorption devices, in the high-power regime where shot and thermal noises can be neglected.
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IWCIT - Statistical characterization of the output of nonlinear power-cubic detection unit for ultrashort light Pulse Communication in the presence of Gaussian noise
2015 Iran Workshop on Communication and Information Theory (IWCIT), 2015Co-Authors: Ranjbar Zefreh, Jawad A. SalehiAbstract:In this paper, an accurate model for the probability density function (pdf) of the random decision variable Y in an ultrafast digital lightwave Communication system, utilizing power-cubic all-optical nonlinear preprocessor is presented. The proposed model can replace the prevalent Gaussian approximation, as the accuracy of the latter is discredited by Monte-Carlo simulation. The Log-Pearson type-3 probability density function (LP3 pdf) is shown to appropriately represents the random decision variable Y. Three characteristic parameters of the LP3 pdf are also obtained through the three moments of the decision variable Y. Finally, the system error probability is revisited using the obtained LP3 pdf of the decision variable, the result of which is in excellent consistency with rigorous Monte-Carlo simulation.
Johannes Partzsch - One of the best experts on this subject based on the ideXlab platform.
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ISCAS - A Pulse Communication flow ready for accelerated neuromorphic experiments
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014Co-Authors: V. Thanasoulis, Bernhard Vogginger, Johannes Partzsch, René SchüffnyAbstract:Large-scale neuromorphic systems demand a sophisticated Communication infrastructure to support several functionalities like configuration of neuron-and-synapse blocks, Pulse stimulation, routing and tracing of the neural activity. This infrastructure is usually implemented around custom-designed FPGA systems. Performance requirements for these systems significantly increase when emulating the biological counterpart at an accelerated timescale. In this paper we characterize the capability of such a system to provide accurate long-term stimulation for emulated spiking networks and tracing of their activity. The design has a capacity of 1 billion timestamped events for both stimulation and tracing with a time resolution up to 48 ns. We characterize the Communication flow in terms of throughput, transmission delay, packet loss and jitter. The results show that the implementation meets the needs of learning experiments, which is an important issue for state-of-the-art neuromorphic systems.
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VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality.
Frontiers in neuroscience, 2011Co-Authors: Stefan Scholze, Bernhard Vogginger, Johannes Partzsch, Stefan Schiefer, Stephan Hartmann, Christian Mayr, Stephan Henker, Sebastian Hoppner, Holger Eisenreich, René SchüffnyAbstract:State-of-the-art large scale neuromorphic systems require sophisticated spike event Communication between units of the neural network. We present a high-speed Communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic Communication ICs in an FPGA-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behaviour of neuromorphic benchmarks. The specialized, dedicated AER Communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based Pulse channel, which transmits configuration data at the full bandwidth otherwise used for Pulse transmission. The overall so-called Pulse Communication subgroup (ICs and FPGA) delivers a factor 25-50 more event transmission rate than other current neuromorphic Communication infrastructures.
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ISCAS - Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011Co-Authors: Stefan Schiefer, Johannes Partzsch, Stephan Hartmann, Stefan Scholze, Christian Mayr, Stephan Henker, René SchüffnyAbstract:Traditionally, the Communication in neuromorphic VLSI systems has been done via parallel asynchronous transmission of Address-Event-Representations (AER) of neuron Pulses. Recently, there has been a move towards greater event transmission speed via a serialization of the AER protocols. We give a live demonstration of a packet based synchronous serial AER infrastructure presented in a recent paper [1], which handles the complete off-wafer Communication and configuration for a newly developed waferscale neuromorphic system [2]1, operating at a factor of 104 faster than biological real-time. Pulse packets are routed from the host PC via Gbit Ethernet to an FPGA board (see Fig. 1), which forwards them to 4 purpose designed Digital Network ASICs (DNCs) on the same board. The DNCs buffer and sort the Pulses, implementing 32 2GBit/s Low Voltage Differential Signaling (LVDS) interfaces to the neuromorphic circuits on the wafer. Pulse Communication to other wafers is done via an FPGA-FPGA Communication using 10Gbit/s Aurora links.
Stefan Schiefer - One of the best experts on this subject based on the ideXlab platform.
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VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality.
Frontiers in neuroscience, 2011Co-Authors: Stefan Scholze, Bernhard Vogginger, Johannes Partzsch, Stefan Schiefer, Stephan Hartmann, Christian Mayr, Stephan Henker, Sebastian Hoppner, Holger Eisenreich, René SchüffnyAbstract:State-of-the-art large scale neuromorphic systems require sophisticated spike event Communication between units of the neural network. We present a high-speed Communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic Communication ICs in an FPGA-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behaviour of neuromorphic benchmarks. The specialized, dedicated AER Communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based Pulse channel, which transmits configuration data at the full bandwidth otherwise used for Pulse transmission. The overall so-called Pulse Communication subgroup (ICs and FPGA) delivers a factor 25-50 more event transmission rate than other current neuromorphic Communication infrastructures.
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ISCAS - Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011Co-Authors: Stefan Schiefer, Johannes Partzsch, Stephan Hartmann, Stefan Scholze, Christian Mayr, Stephan Henker, René SchüffnyAbstract:Traditionally, the Communication in neuromorphic VLSI systems has been done via parallel asynchronous transmission of Address-Event-Representations (AER) of neuron Pulses. Recently, there has been a move towards greater event transmission speed via a serialization of the AER protocols. We give a live demonstration of a packet based synchronous serial AER infrastructure presented in a recent paper [1], which handles the complete off-wafer Communication and configuration for a newly developed waferscale neuromorphic system [2]1, operating at a factor of 104 faster than biological real-time. Pulse packets are routed from the host PC via Gbit Ethernet to an FPGA board (see Fig. 1), which forwards them to 4 purpose designed Digital Network ASICs (DNCs) on the same board. The DNCs buffer and sort the Pulses, implementing 32 2GBit/s Low Voltage Differential Signaling (LVDS) interfaces to the neuromorphic circuits on the wafer. Pulse Communication to other wafers is done via an FPGA-FPGA Communication using 10Gbit/s Aurora links.
Stefan Scholze - One of the best experts on this subject based on the ideXlab platform.
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VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality.
Frontiers in neuroscience, 2011Co-Authors: Stefan Scholze, Bernhard Vogginger, Johannes Partzsch, Stefan Schiefer, Stephan Hartmann, Christian Mayr, Stephan Henker, Sebastian Hoppner, Holger Eisenreich, René SchüffnyAbstract:State-of-the-art large scale neuromorphic systems require sophisticated spike event Communication between units of the neural network. We present a high-speed Communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic Communication ICs in an FPGA-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behaviour of neuromorphic benchmarks. The specialized, dedicated AER Communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based Pulse channel, which transmits configuration data at the full bandwidth otherwise used for Pulse transmission. The overall so-called Pulse Communication subgroup (ICs and FPGA) delivers a factor 25-50 more event transmission rate than other current neuromorphic Communication infrastructures.
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ISCAS - Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011Co-Authors: Stefan Schiefer, Johannes Partzsch, Stephan Hartmann, Stefan Scholze, Christian Mayr, Stephan Henker, René SchüffnyAbstract:Traditionally, the Communication in neuromorphic VLSI systems has been done via parallel asynchronous transmission of Address-Event-Representations (AER) of neuron Pulses. Recently, there has been a move towards greater event transmission speed via a serialization of the AER protocols. We give a live demonstration of a packet based synchronous serial AER infrastructure presented in a recent paper [1], which handles the complete off-wafer Communication and configuration for a newly developed waferscale neuromorphic system [2]1, operating at a factor of 104 faster than biological real-time. Pulse packets are routed from the host PC via Gbit Ethernet to an FPGA board (see Fig. 1), which forwards them to 4 purpose designed Digital Network ASICs (DNCs) on the same board. The DNCs buffer and sort the Pulses, implementing 32 2GBit/s Low Voltage Differential Signaling (LVDS) interfaces to the neuromorphic circuits on the wafer. Pulse Communication to other wafers is done via an FPGA-FPGA Communication using 10Gbit/s Aurora links.
