14,000,000 Leading Edge Experts on the ideXlab platform

Scan Science and Technology

Contact Leading Edge Experts & Companies

Scan Science and Technology

Contact Leading Edge Experts & Companies

The Experts below are selected from a list of 365121 Experts worldwide ranked by ideXlab platform

K Scheerschmidt - One of the best experts on this subject based on the ideXlab platform.

Kai Zoschke - One of the best experts on this subject based on the ideXlab platform.

  • LiTaO3 Capping Technology for Wafer Level Chip Size Packaging of SAW Filters
    2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016
    Co-Authors: Kai Zoschke, Matthias Wegner, Richard Gruenwald, Clemens Schoenbein, Christina Lopper, M. Klein, Klaus-dieter Lang

    In this paper we present a novel low-cost wafer level packaging technology for surface acoustic wave (SAW) filter devices which provides quasi-hermetic device sealing and full compatibility to surface mount assembly technology. The wafer level packaging concept is based on sealing each sensitive SAW structure with a LiTaO3 cap while keeping the peripheral IO pads of the devices accessible. To enable such a process scheme LiTaO3 posts with adhesive bonding frames were pre-processed from LiTaO3 Wafers and subsequently bonded to the SAW device Wafers using thermo-compression type wafer-to-wafer bonding processes. Subsequently, the Wafers with the pre-processed post structures were back-ground to separate the bonded cap structures on the device Wafers. A subsequent balling of the peripheral pads with pre-formed SAC305 solder balls finalized the wafer level processing. The process was developed using 403 MHz SAW devices for MICS (Medical Implant Communication Service) band application. Process flow for fabrication and assembly of the SAW filter CSPs with final dimensions of 1.7 x 1.5 x 0.45 mm3 as well as the measured electrical performance will be discussed in the paper. Additionally, options for process modifications regarding size and cost reduction will be presented.

  • Application of TSV integration and wafer bonding technologies for hermetic wafer level packaging of MEMS components for miniaturized timing devices
    2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015
    Co-Authors: Kai Zoschke, Charles-alix Manier, James Dekker, David Ruffieux, Giorgio Allegato, Martin Wilke, Hermann Dr.-ing. Oppermann, A. Jaakkola, S. Dalla Piazza, Klaus-dieter Lang

    The paper presents different approaches for hermetic wafer level packaging of oscillator components like quartz crystals or silicon resonators. The proposed concepts involve technologies like TSV formation into passive or active silicon Wafers, formation of proper bond frames on interposer, ASIC or cap Wafers as well as hermetic bonding using AuSn soldering either in wafer to wafer style or with reconfigured components on a carrier wafer.

  • Hermetic wafer level packaging of MEMS components using through silicon via and wafer to wafer bonding technologies
    2013 IEEE 63rd Electronic Components and Technology Conference, 2013
    Co-Authors: Kai Zoschke, Charles-alix Manier, Hannele Heikkinen, James Dekker, David Ruffieux, M. Wilke, Nils Jürgensen, Dalla S. Piazza, Hermann Oppermann, Giorgio Allegato

    This paper presents the fabrication steps of a MEMS package based on silicon interposer Wafers with copper filled TSVs and bonded cap Wafers for hermetic sealing of resonator components. All processes were performed at 200 mm wafer level. For interposer fabrication a standard process flow including silicon blind hole etching, isolation, copper filling, wafer front side redistribution, support wafer bonding, wafer thinning, and TSV backside reveal was applied. As interposer backside metallization, appropriate I/O terminals and seal ring structures were deposited by semi-additive Au and Au+Sn electro plating. Following, getter material was deposited onto the interposer Wafers which were 90 μm thick and still mounted onto carrier Wafers. Subsequently, the I/O terminal pads of the interposer were stud bumped and finally more than 5000 quartz resonator components were assembled onto each interposer wafer by Au-Au direct metal bonding. The cap wafer was equipped with 200 μm deep dry etched cavities and electro plated Au seal rings around them. Finally, both cap and interposer Wafers were bonded together using a wafer to wafer bonder and an adapted AuSn soldering process scheme. In a last step, the carrier wafer was removed from the former front side of the interposer wafer and wafer level testing was performed. From a total of 4824 tested devices we found that more than 75 % were sealed properly under vacuum. The getter appears to be effective leading to ~0.1 mbar equivalent air pressure and cavities without getter appear to reach residual air pressure between 1-2 mbar. The used fabrication processes and final results will be discussed detailed in this manuscript.

  • Temporary and Permanent Adhesives for Thin Wafer Handling and Assembly
    Co-Authors: Mark S. Oliver, Matthias Wegner, Kai Zoschke, Jong-uk Kim, Zidong Wang, Janet Okada, Elissei Iagodkine, Gallagher Michael K, Michael Töpper

    Temporary wafer bonding has emerged as the method of choice for handling silicon Wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, excellent thermal stability, and clean room-temperature release directly from the device wafer. We will present successful temporary wafer bonding using a new BCB (benzocyclobutene)-based material that can meet these requirements. For this temporary wafer bonding technology, wafer preparation involves spin coating the device wafer with the BCB-based adhesive to a thickness of up to 100 μm and spin coating the carrier wafer with an adhesion promoter. The Wafers can then be bonded at temperatures as low as 80 °C for as short as 30 seconds. The low bonding temperature means the Wafers can be loaded into a preheated wafer bonding to...

  • evaluation of thin wafer processing using a temporary wafer handling system as key technology for 3d system integration
    Electronic Components and Technology Conference, 2010
    Co-Authors: Kai Zoschke, Matthias Wegner, Christina Lopper, Martin Wilke, N Jurgensen, I Kuna, V Glaw, J Roder, O Wunsch, M J Wolf

    In this paper we describe the process integration of a temporary wafer handling system for wafer thinning and thin wafer backside processing. Thin wafer handling is a key technology and enabler for the wafer level fabrication of through silicon via (TSV) based 3D architectures. The work was done as evaluation study to prove the compatibility of a thin wafer handling system with standard processes used for thinning and backside processing of “via-first” TSV Wafers as well as for thinning of bumped Wafers. The used thin wafer handling system is based on perforated carrier Wafers, which are bonded by an adhesive to the customer wafer and de-bonded by solvent release of the adhesive. All Wafers used in this work had 200 mm format. The evaluation was run systematically in three major phases. In the first phase the main process scenarios, which require thin wafer handling, were defined. In a second phase setup trials for bonding, thinning, backside processing and de-bonding were run on monitor Wafers with different types of front side topography, but without TSVs. After finishing the setup trials in a third phase, the monitor Wafers were replaced by Wafers with copper filled TSVs, which were fabricated in “via-first” technology. Using the established thin wafer handling and processing sequence, silicon interposer Wafers with 55 µm thickness were manufactured. The measured via chains have via pitches of 28 µm using 15 µm via diameter.

Kensall D. Wise - One of the best experts on this subject based on the ideXlab platform.

  • Low-temperature silicon wafer-to-wafer bonding using gold at eutectic temperature
    Sensors and Actuators A: Physical, 1994
    Co-Authors: Reinoud F. Wolffenbuttel, Kensall D. Wise

    Abstract Micromechanical smart sensor and actuator systems of high complexity become commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different Wafers and one of the Wafers is dedicated to contain the readout circuits. The individually-processed Wafers can be assembled using wafer-to-wafer bonding and can be combined to one single functional electro-mechanical unit using through-wafer interconnect, provided that the processes involved comply with the constraints imposed by the proper operation of the active electrical and micromechanical subsystems. This implies low-temperature wafer-to-wafer bonding and through-wafer interconnect. Au/Si eutectic bonding has been investigated as it can conveniently be combined with bulk-micromachined through-wafer interconnect. The temperature control in eutectic bonding has been shown to be critical.

U Gosele - One of the best experts on this subject based on the ideXlab platform.

  • semiconductor wafer bonding science and technology
    Co-Authors: Q Y Tong, U Gosele

    Basics of Interactions Between Flat Surfaces. Influence of Particles, Surface Steps, and Cavities. Surface Preparation and Room-Temperature Wafer Bonding. Thermal Treatment of Bonded Wafer Pairs. Thinning Procedures. Electrical Properties of Bonding Interfaces. Stresses in Bonded Wafers. Bonding of Dissimilar Materials. Bonding of Structured Wafers. Mainstream Applications. Emerging and Future Applications. Index.

  • self propagating room temperature silicon wafer bonding in ultrahigh vacuum
    Applied Physics Letters, 1995
    Co-Authors: U Gosele, H Stenzel, T Martini, J Steinkirchner, D Conrad, K Scheerschmidt

    Wafer bonding of commercial 4 in. silicon Wafers has been performed at room temperature under ultrahigh vacuum conditions. After local initiation of the bonding process the bonding area is self‐propagating just as in the case of wafer bonding under atmospheric conditions. The room‐temperature bonded Wafers, without any additional heat treatment show a bonding strength typical for bulk material.

Emanuel M Sachs - One of the best experts on this subject based on the ideXlab platform.

  • crack detection in crystalline silicon solar cells using dark field imaging
    Energy Procedia, 2017
    Co-Authors: Sarah Wieghold, Ashley E Morishige, Luke T Meyer, Tonio Buonassisi, Emanuel M Sachs

    Abstract The high capital expenditure (capex) necessary to manufacture crystalline silicon PV modules negatively affects the levelized cost of electricity (¢/kWh) and critically impacts the rate at which the PV industry can scale up. Wafer, cell, and module fabrication with thin free-standing silicon Wafers is one key to reduce capex. Thin Wafers reduce capex associated with silicon refining and wafer fabrication, which together sum to 58% of the total capex of silicon module manufacturing. In addition, thin Wafers directly and significantly reduce variable costs. However, introducing 50 μm thin free-standing Wafers into today’s manufacturing lines result in cracking, creating a yield-based disincentive. Due to the brittle nature of silicon, wafer breakage is the major concern due to the high stress that is induced during processes in manufacturing lines. In this paper, we describe an improved method for edge micro-crack detection that can help enable low-capex, thin free-standing Si Wafers. We present a method of detecting and measuring cracks along wafer edges by using a dark-field IR scattering imaging technique which enables detection of edge cracks at the micron scale.