The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Markku Renfors - One of the best experts on this subject based on the ideXlab platform.
-
Advanced techniques on multiRate signal processing for digital information processing [Editorial]
Signal Processing IET, 2011Co-Authors: Massimiliano Laddomada, Ching Lim Yong, Fa-long Luo, Gordana Jovanovic Dolecek, Markku Renfors, L. WanhammarAbstract:MultiRate signal processing has become a key topic enabling efficient techniques for digital information processing in a variety of applications such as digital transceivers s for wireless as well as satellite communication systems, digital broadcasting, high performance audio and video, multimedia services, and signal compression. In the wireless communications arena, multiRate signal processing techniques provide effective means to implement flexible receiver channelisation filtering and sampling Rate Conversion for software and cognitive radio digital frontends. As far as multimedia signal processing is concerned, recent techniques relying on multiRate filter banks have resulted in improved subband coding techniques reflected in the JPEG-2000 multimedia standard, as well as on some modern audio compression formats such as MP3, AAC3 and ATRAC3plus, to cite but a few.
-
decimation by non integer factor in multistandard radio receivers
Signal Processing, 2005Co-Authors: Dušan Babič, Markku RenforsAbstract:In many applications it is required to have a system for non-integer sampling Rate Conversion (SRC), which supports any decimation factor, and provides enough attenuation for aliasing and imaging signal components. A good example case is a software radio receiver, where the ratio of sampling Rate just after A/D converter and symbol Rate for a supported standard may be a ratio of two large mutually prime numbers. In a digital mobile receiver, it is very important to reduce the power consumption. The power consumption in context of SRC can be reduced by designing a system that has low Rate of multiplication and addition operations.This paper introduces a novel non-integer decimation method. The proposed structure is a combination of an FIR filter and a polynomial-based interpolation filter. For the special case based on a cascaded integrator-comb (CIC) filter and simple polynomial-based interpolation filter, the proposed combination has a very efficient implementation structure. The results shown in this paper indicate that the computational complexity and multiplication Rate can be reduced compared to the earlier solutions.
-
discrete time modeling of polynomial based interpolation filters in rational sampling Rate Conversion
International Symposium on Circuits and Systems, 2003Co-Authors: D Babic, Vesa Lehtinen, Markku RenforsAbstract:If sampling Rate Conversion (SRC) is performed between arbitrary sampling Rates, then the SRC factor can be a ratio of two very large integers or even an irrational number. An efficient way to reduce the implementation complexity of a SRC system in those cases is to use polynomial-based interpolation filters that mimic digitally the hybrid analogue/digital system. In practice, the sampling Rate Conversion is approximated with a rational factor. In this case, the hybrid analogue/digital model used to represent the SRC process may be represented by an equivalent discrete-time model. The discrete-time modeling of the rational SRC has been used earlier for the zeroth order interpolation. This paper extends this idea to arbitrary polynomial-based interpolation. Furthermore, this paper derives the relation between various polynomial-based interpolation filters (Farrow structure and its modifications) and polyphase FIR model filters. This paper observes possible applications of these relations, such as filter design, implementation complexity reduction, and response distortion analysis.
-
decimation by non integer factor in software radio receivers
Facta universitatis. Series electronics and energetics, 2003Co-Authors: Dušan Babič, Markku RenforsAbstract:The sampling Rate Conversion is a critical functionality of the software radio receiver. Because the signals of different system standards have incommensuRate symbol/sampling Rates and a common Analog-to Digital Converter (ADC) is to be used for all supported standards, the decimation factor may become very difficult non-integer number. This paper gives overviews and comparisons of two efficient fractional decimator structures based on Cascaded Integrator-Comb (CIC) filters and low order polynomialbased interpolation filters.
-
decimation by irrational factor using cic filter and linear interpolation
International Conference on Acoustics Speech and Signal Processing, 2001Co-Authors: D Babic, Jussi Vesma, Markku RenforsAbstract:This paper presents an efficient way to implement flexible multiRate signal processing systems with high oversampling ratio and adjustable fractional or irrational sampling Rate Conversion ratio. One application area is a multi-standard communication receiver which should be adjustable for different symbol Rates utilized in different systems. The proposed decimation filter consists of parallel CIC (cascaded integrator-comb) filters followed by a linear interpolation filter. The idea is to use two parallel CIC filters to calculate the two needed sample values for linear interpolation. These samples occur just before and after the final output sample. This corresponds to a system where the linear interpolation is done at the higher input sampling Rate.
Gerhard Fettweis - One of the best experts on this subject based on the ideXlab platform.
-
sample Rate Conversion for software radio
IEEE Communications Magazine, 2000Co-Authors: Tim Hentschel, Gerhard FettweisAbstract:Software radio terminals must be able to process many various communications standards. These standards are generally based on different master clock Rates and thus employ different bit/chip Rates. The most obvious solution to cope with the diversity of master clock Rates in one terminal is to provide a dedicated master clock for each standard of operation. Not only too costly, this kind of solution limits the applicability of a realized terminal. Hence, it is much more elegant to run the terminal on a fixed clock Rate, and perform digital sample Rate Conversion controlled by software.
A Hjorungnes - One of the best experts on this subject based on the ideXlab platform.
-
generalized symbol synchronization using variable iir and fir fractional delay filters with arbitrary oversampling ratios
International Conference on Acoustics Speech and Signal Processing, 2004Co-Authors: M Makundi, T L Laakso, A HjorungnesAbstract:A generalized maximum likelihood symbol synchronization scheme is proposed. It enables use of variable fractional-delay (interpolation) filters when the desired sampling Rate Conversion factor is non-integer or time varying. Furthermore, both IIR and FIR type variable filter structures can be used in efficient configurations. The paper includes both performance analysis and discussion of implementation complexity.
H. Murakami - One of the best experts on this subject based on the ideXlab platform.
-
Block sampling Rate Conversion systems using real-valued fast cyclic convolution algorithms
IEEE Transactions on Signal Processing, 1997Co-Authors: H. MurakamiAbstract:The real-valued transform is related to the polyphase decomposition of a sequence. This observation is applied for deriving sampling Rate Conversion systems that are implemented by the real-valued fast cyclic convolution algorithms. The systems include interpolation by an integer factor, decimation by an integer factor, and sampling Rate Conversion by a rational factor. The proposed implementations are useful when the signals and impulse responses of filters are restricted to be real.
Moreno Arostegui, Jua Manuel - One of the best experts on this subject based on the ideXlab platform.
-
An architecture for real-time arbitrary and variable sampling Rate Conversion with application to the processing of harmonic signals
2020Co-Authors: Galindo Guarch, Francisco Javie, Audrenghie Philippe, Moreno Arostegui, Jua ManuelAbstract:The paper presents a new solution for sampling Rate Conversion and processing of harmonic signals with known but possibly varying fundamental frequency. This problem is commonly found in particle accelerators, for tracking the beam signals whose revolution frequency varies during the acceleration ramp. It is also common among many other fields such as speech and music processing, removal of mechanical noises, filtering of biomedical recordings, active crack imaging, etc. The key element in the proposed solution is a new architecture for a Farrow-based resampler, in which the resampling ratio can take any value and can be modified continuously to follow the signal fundamental frequency. The combination of two complementary resamplers creates a processing region where signal synchronous processing is performed. The resampler architecture is optimized for modern FPGA features. It decouples the processing and sampling clocks, and uses a single processing (hardware) clock whose frequency remains fixed. The functional model was migRated to Xilinx System Generator and the overall performance is evaluated with an application that filters a periodic signal whose frequency follows a known linear ramp in the presence of additive white noise.The authors would like to thank CERN colleagues in BE-RF-FB section, plus K. Smith’s group at BNL, T. Mastoridis at California Polytechnic State University, C. Rivetta at SLAC and F. Tamura from J-PARC for the many fruitful discussions. Special thanks to A. Butterworth and R. Borner at CERN BE-RF for proofreading the paper.Peer Reviewe
-
An architecture for real-time arbitrary and variable sampling Rate Conversion with application to the processing of harmonic signals
'Institute of Electrical and Electronics Engineers (IEEE)', 2020Co-Authors: Galindo Guarch, Francisco Javie, Audrenghie Philippe, Moreno Arostegui, Jua ManuelAbstract:The paper presents a new solution for sampling Rate Conversion and processing of harmonic signals with known but possibly varying fundamental frequency. This problem is commonly found in particle accelerators, for tracking the beam signals whose revolution frequency varies during the acceleration ramp. It is also common among many other fields such as speech and music processing, removal of mechanical noises, filtering of biomedical recordings, active crack imaging, etc. The key element in the proposed solution is a new architecture for a Farrow-based resampler, in which the resampling ratio can take any value and can be modified continuously to follow the signal fundamental frequency. The combination of two complementary resamplers creates a processing region where signal synchronous processing is performed. The resampler architecture is optimized for modern FPGA features. It decouples the processing and sampling clocks, and uses a single processing (hardware) clock whose frequency remains fixed. The functional model was migRated to Xilinx System Generator and the overall performance is evaluated with an application that filters a periodic signal whose frequency follows a known linear ramp in the presence of additive white noise.The authors would like to thank CERN colleagues in BE-RF-FB section, plus K. Smith’s group at BNL, T. Mastoridis at California Polytechnic State University, C. Rivetta at SLAC and F. Tamura from J-PARC for the many fruitful discussions. Special thanks to A. Butterworth and R. Borner at CERN BE-RF for proofreading the paper.Peer ReviewedPostprint (published version
-
An Architecture for Real-Time Arbitrary and Variable Sampling Rate Conversion With Application to the Processing of Harmonic Signals
'Institute of Electrical and Electronics Engineers (IEEE)', 2020Co-Authors: Guarch, Fco Javie Galindo, Audrenghie Philippe, Moreno Arostegui, Jua ManuelAbstract:The paper presents a new solution for sampling Rate Conversion and processing of harmonic signals with known but possibly varying fundamental frequency. This problem is commonly found in particle accelerators, for tracking the beam signals whose revolution frequency varies during the acceleration ramp. It is also common among many other fields such as speech and music processing, removal of mechanical noises, filtering of biomedical recordings, active crack imaging, etc. The key element in the proposed solution is a new architecture for a Farrow-based resampler, in which the resampling ratio can take any value and can be modified continuously to follow the signal fundamental frequency. The combination of two complementary resamplers creates a processing region where signal synchronous processing is performed. The resampler architecture is optimized for modern FPGA features. It decouples the processing and sampling clocks, and uses a single processing (hardware) clock whose frequency remains fixed. The functional model was migRated to Xilinx System Generator and the overall performance is evaluated with an application that filters a periodic signal whose frequency follows a known linear ramp in the presence of additive white noiseThe paper presents a new solution for sampling Rate Conversion and processing of harmonic signals with known but possibly varying fundamental frequency. This problem is commonly found in particle accelerators, for tracking the beam signals whose revolution frequency varies during the acceleration ramp. It is also common among many other fields such as speech and music processing, removal of mechanical noises, filtering of biomedical recordings, active crack imaging, etc. The key element in the proposed solution is a new architecture for a Farrow-based resampler, in which the resampling ratio can take any value and can be modified continuously to follow the signal fundamental frequency. The combination of two complementary resamplers creates a processing region where signal synchronous processing is performed. The resampler architecture is optimized for modern FPGA features. It decouples the processing and sampling clocks, and uses a single processing (hardware) clock whose frequency remains fixed. The functional model was migRated to Xilinx System Generator and the overall performance is evaluated with an application that filters a periodic signal whose frequency follows a known linear ramp in the presence of additive white noise
