The Experts below are selected from a list of 324 Experts worldwide ranked by ideXlab platform
Peter R. Kinget - One of the best experts on this subject based on the ideXlab platform.
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a self duty cycled and synchronized uwb pulse Radio Receiver soc with automatic threshold recovery based demodulation
IEEE Journal of Solid-state Circuits, 2014Co-Authors: Baradwaj Vigraham, Peter R. KingetAbstract:A fully self-duty-cycled and synchronized UWB pulse-Radio Receiver SoC targeted at low-data-rate communication is presented. The Receiver uses pulse-Radio UWB in the 3.6-5 GHz band to achieve a high energy efficiency. The proposed architecture employs a a demodulator with an automatic analog threshold-recovery and an all-digital clock-and-data-recovery synchronizer. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a -79.5 dBm, 1 Mbps-normalized sensitivity for a mere 375 pJ/bit of power consumption in 65 nm LP CMOS, with aggressive duty-cycling ( ≈30 ns ON times) combined with bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components.
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A 3.1–9.5 GHz agile UWB pulse Radio Receiver with discrete-time wideband-IF correlation in 90nm CMOS
2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008Co-Authors: F. Zhang, Ranjit Gharpurey, Peter R. KingetAbstract:An 8-channel 3.1-9.5 GHz UWB pulse Radio Receiver is realized using a double-conversion architecture with discrete-time wideband IF correlation. The pulse templates for correlation are pre-stored in memories which allows fast band switching and agile interferer avoidance since no PLL resettling is required. The Receiver chip is implemented in a standard 90 nm CMOS process and occupies 1 mm2.
Asad A. Abidi - One of the best experts on this subject based on the ideXlab platform.
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The Path to the Software-Defined Radio Receiver
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Asad A. AbidiAbstract:After being the subject of speculation for many years, a software-defined Radio Receiver concept has emerged that is suitable for mobile handsets. A key step forward is the realization that in mobile handsets, it is enough to receive one channel with any bandwidth, situated in any band. Thus, the front-end can be tuned electronically. Taking a cue from a digital front-end, the Receiver's flexible analog baseband samples the channel of interest at zero IF, and is followed by clock-programmable downsampling with embedded filtering. This gives a tunable selectivity that exceeds that of an RF prefilter, and a conversion rate that is low enough for A/D conversion at only milliwatts. The front-end consists of a wideband low noise amplifier and a mixer tunable by a wideband LO. A 90-nm CMOS prototype tunes 200 kHz to 20-MHz-wide channels located anywhere from 800 MHz to 6 GHz
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Software-defined Radio Receiver: dream to reality
IEEE Communications Magazine, 2006Co-Authors: R. Bagheri, Ahmad Mirzaei, Mohammad E. Heidari, Saeed Chehrazi, Mohyee Mikhemar, Wai Tang, Asad A. AbidiAbstract:This article describes a fully integrated 90 nm CMOS software-defined Radio Receiver operating in the 800 MHz to 5 GHz band. Unlike the classical SDR paradigm, which digitizes the whole spectrum uniformly, this Receiver acts as a signal conditioner for the analog-to-digital converters, emphasizing only the wanted channel. Thus, the ADCs operate with modest resolution and sample rate, consuming low power. This approach makes portable SDR a reality
F. Zhang - One of the best experts on this subject based on the ideXlab platform.
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A 3.1–9.5 GHz agile UWB pulse Radio Receiver with discrete-time wideband-IF correlation in 90nm CMOS
2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008Co-Authors: F. Zhang, Ranjit Gharpurey, Peter R. KingetAbstract:An 8-channel 3.1-9.5 GHz UWB pulse Radio Receiver is realized using a double-conversion architecture with discrete-time wideband IF correlation. The pulse templates for correlation are pre-stored in memories which allows fast band switching and agile interferer avoidance since no PLL resettling is required. The Receiver chip is implemented in a standard 90 nm CMOS process and occupies 1 mm2.
Tayfun Nesimoglu - One of the best experts on this subject based on the ideXlab platform.
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software defined Radio Receiver test bed
Vehicular Technology Conference, 2001Co-Authors: J R Macleod, Mark A Beach, Paul A Warr, Tayfun NesimogluAbstract:This paper identifies the issues that are important in the design of a SDR Receiver. Receiver architectures are first discussed, and the conclusion drawn that the conventional superheterodyne structure is most appropriate for a SDR Receiver. Issues associated with image rejection, and Receiver linearity are discussed. The design of a sweepable preselect filter is discussed in detail. Design considerations for a practical SDR test-bed are presented.
Baradwaj Vigraham - One of the best experts on this subject based on the ideXlab platform.
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a self duty cycled and synchronized uwb pulse Radio Receiver soc with automatic threshold recovery based demodulation
IEEE Journal of Solid-state Circuits, 2014Co-Authors: Baradwaj Vigraham, Peter R. KingetAbstract:A fully self-duty-cycled and synchronized UWB pulse-Radio Receiver SoC targeted at low-data-rate communication is presented. The Receiver uses pulse-Radio UWB in the 3.6-5 GHz band to achieve a high energy efficiency. The proposed architecture employs a a demodulator with an automatic analog threshold-recovery and an all-digital clock-and-data-recovery synchronizer. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a -79.5 dBm, 1 Mbps-normalized sensitivity for a mere 375 pJ/bit of power consumption in 65 nm LP CMOS, with aggressive duty-cycling ( ≈30 ns ON times) combined with bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components.
