The Experts below are selected from a list of 924 Experts worldwide ranked by ideXlab platform
Nikolaos Papandreou - One of the best experts on this subject based on the ideXlab platform.
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open block characterization and Read Voltage calibration of 3d qlc nand flash
International Reliability Physics Symposium, 2020Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Nikolas Ioannou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Patrick Breen, Gary A TresslerAbstract:3D QLC NAND has recently entered the SSD market offering capacity increase and cost reduction compared to 3D TLC NAND. However, the endurance of QLC NAND is limited. Moreover, due to reduction of the available margin between the programmed threshold Voltage distributions, QLC NAND is more susceptible to bit errors. Read Voltage calibration is a key element of modern NAND flash memory controllers to improve the overall bit-error rate and maintain enterprise level reliability. To reduce the calibration overhead associated with the increased number of pages and Read Voltages in QLC NAND, page grouping is an effective approach. This paper presents open block characterization and Read Voltage calibration results of state-of-the-art 3D QLC NAND. We present experimental measurements of the bit-error characteristics and threshold Voltage distributions based on closed and open block test patterns. We discuss the reliability issues with open blocks in preserving uniform characteristics within a page group at the boundary programmed layer and analyze the performance of different calibration algorithms.
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IRPS - Open Block Characterization and Read Voltage Calibration of 3D QLC NAND Flash
2020 IEEE International Reliability Physics Symposium (IRPS), 2020Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Patrick Breen, Ioannou Nikolas, Gary A TresslerAbstract:3D QLC NAND has recently entered the SSD market offering capacity increase and cost reduction compared to 3D TLC NAND. However, the endurance of QLC NAND is limited. Moreover, due to reduction of the available margin between the programmed threshold Voltage distributions, QLC NAND is more susceptible to bit errors. Read Voltage calibration is a key element of modern NAND flash memory controllers to improve the overall bit-error rate and maintain enterprise level reliability. To reduce the calibration overhead associated with the increased number of pages and Read Voltages in QLC NAND, page grouping is an effective approach. This paper presents open block characterization and Read Voltage calibration results of state-of-the-art 3D QLC NAND. We present experimental measurements of the bit-error characteristics and threshold Voltage distributions based on closed and open block test patterns. We discuss the reliability issues with open blocks in preserving uniform characteristics within a page group at the boundary programmed layer and analyze the performance of different calibration algorithms.
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reliability of 3d nand flash memory with a focus on Read Voltage calibration from a system aspect
Non-Volatile Memory Technology Symposium, 2019Co-Authors: Nikolaos Papandreou, Nikolas Ioannou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Haralampos PozidisAbstract:This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the Read Voltage calibration and its critical role in achieving low error-rates and low latency Read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and Read-disturb from different Read Voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.
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NVMTS - Reliability of 3D NAND flash memory with a focus on Read Voltage calibration from a system aspect
2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 2019Co-Authors: Nikolaos Papandreou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Ioannou Nikolas, Haralampos PozidisAbstract:This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the Read Voltage calibration and its critical role in achieving low error-rates and low latency Read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and Read-disturb from different Read Voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.
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IRPS - Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory
2019 IEEE International Reliability Physics Symposium (IRPS), 2019Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Roman A Pletka, Sasa Tomic, Patrick Breen, Gary A Tressler, Ioannou Nikolas, Aaron D. Fry, Timothy J. FisherAbstract:3D NAND flash memory has entered dynamically into the space of enterprise server and storage systems, offering significantly higher capacity and better endurance than the latest 2D technology node. Moreover, the advancements in vertical stacking, cell design and program/Read algorithms, have also enabled TLC 3D NAND flash with enterprise-level reliability, thus achieving further increase in capacity and cost-per-bit reduction. This paper presents an in-depth analysis of the bit-error characteristics of state-of-the-art 64-layer 3D TLC NAND flash with a focus on Read-Voltage calibration. We provide experimental measurements of the RBER and threshold Voltage distributions using typical and mixed-mode test patterns of program/erase cycling, retention and Read-disturb. Moreover, we quantify the RBER components attributed to threshold Voltage level overlapping and on-chip 2-step program errors. Finally, we characterize how the optimal Read Voltages change under different device stress and we evaluate calibration schemes with different performance and complexity trade-offs.
Haralampos Pozidis - One of the best experts on this subject based on the ideXlab platform.
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open block characterization and Read Voltage calibration of 3d qlc nand flash
International Reliability Physics Symposium, 2020Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Nikolas Ioannou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Patrick Breen, Gary A TresslerAbstract:3D QLC NAND has recently entered the SSD market offering capacity increase and cost reduction compared to 3D TLC NAND. However, the endurance of QLC NAND is limited. Moreover, due to reduction of the available margin between the programmed threshold Voltage distributions, QLC NAND is more susceptible to bit errors. Read Voltage calibration is a key element of modern NAND flash memory controllers to improve the overall bit-error rate and maintain enterprise level reliability. To reduce the calibration overhead associated with the increased number of pages and Read Voltages in QLC NAND, page grouping is an effective approach. This paper presents open block characterization and Read Voltage calibration results of state-of-the-art 3D QLC NAND. We present experimental measurements of the bit-error characteristics and threshold Voltage distributions based on closed and open block test patterns. We discuss the reliability issues with open blocks in preserving uniform characteristics within a page group at the boundary programmed layer and analyze the performance of different calibration algorithms.
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IRPS - Open Block Characterization and Read Voltage Calibration of 3D QLC NAND Flash
2020 IEEE International Reliability Physics Symposium (IRPS), 2020Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Patrick Breen, Ioannou Nikolas, Gary A TresslerAbstract:3D QLC NAND has recently entered the SSD market offering capacity increase and cost reduction compared to 3D TLC NAND. However, the endurance of QLC NAND is limited. Moreover, due to reduction of the available margin between the programmed threshold Voltage distributions, QLC NAND is more susceptible to bit errors. Read Voltage calibration is a key element of modern NAND flash memory controllers to improve the overall bit-error rate and maintain enterprise level reliability. To reduce the calibration overhead associated with the increased number of pages and Read Voltages in QLC NAND, page grouping is an effective approach. This paper presents open block characterization and Read Voltage calibration results of state-of-the-art 3D QLC NAND. We present experimental measurements of the bit-error characteristics and threshold Voltage distributions based on closed and open block test patterns. We discuss the reliability issues with open blocks in preserving uniform characteristics within a page group at the boundary programmed layer and analyze the performance of different calibration algorithms.
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reliability of 3d nand flash memory with a focus on Read Voltage calibration from a system aspect
Non-Volatile Memory Technology Symposium, 2019Co-Authors: Nikolaos Papandreou, Nikolas Ioannou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Haralampos PozidisAbstract:This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the Read Voltage calibration and its critical role in achieving low error-rates and low latency Read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and Read-disturb from different Read Voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.
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NVMTS - Reliability of 3D NAND flash memory with a focus on Read Voltage calibration from a system aspect
2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 2019Co-Authors: Nikolaos Papandreou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Ioannou Nikolas, Haralampos PozidisAbstract:This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the Read Voltage calibration and its critical role in achieving low error-rates and low latency Read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and Read-disturb from different Read Voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.
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IRPS - Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory
2019 IEEE International Reliability Physics Symposium (IRPS), 2019Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Roman A Pletka, Sasa Tomic, Patrick Breen, Gary A Tressler, Ioannou Nikolas, Aaron D. Fry, Timothy J. FisherAbstract:3D NAND flash memory has entered dynamically into the space of enterprise server and storage systems, offering significantly higher capacity and better endurance than the latest 2D technology node. Moreover, the advancements in vertical stacking, cell design and program/Read algorithms, have also enabled TLC 3D NAND flash with enterprise-level reliability, thus achieving further increase in capacity and cost-per-bit reduction. This paper presents an in-depth analysis of the bit-error characteristics of state-of-the-art 64-layer 3D TLC NAND flash with a focus on Read-Voltage calibration. We provide experimental measurements of the RBER and threshold Voltage distributions using typical and mixed-mode test patterns of program/erase cycling, retention and Read-disturb. Moreover, we quantify the RBER components attributed to threshold Voltage level overlapping and on-chip 2-step program errors. Finally, we characterize how the optimal Read Voltages change under different device stress and we evaluate calibration schemes with different performance and complexity trade-offs.
Gary A Tressler - One of the best experts on this subject based on the ideXlab platform.
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open block characterization and Read Voltage calibration of 3d qlc nand flash
International Reliability Physics Symposium, 2020Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Nikolas Ioannou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Patrick Breen, Gary A TresslerAbstract:3D QLC NAND has recently entered the SSD market offering capacity increase and cost reduction compared to 3D TLC NAND. However, the endurance of QLC NAND is limited. Moreover, due to reduction of the available margin between the programmed threshold Voltage distributions, QLC NAND is more susceptible to bit errors. Read Voltage calibration is a key element of modern NAND flash memory controllers to improve the overall bit-error rate and maintain enterprise level reliability. To reduce the calibration overhead associated with the increased number of pages and Read Voltages in QLC NAND, page grouping is an effective approach. This paper presents open block characterization and Read Voltage calibration results of state-of-the-art 3D QLC NAND. We present experimental measurements of the bit-error characteristics and threshold Voltage distributions based on closed and open block test patterns. We discuss the reliability issues with open blocks in preserving uniform characteristics within a page group at the boundary programmed layer and analyze the performance of different calibration algorithms.
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IRPS - Open Block Characterization and Read Voltage Calibration of 3D QLC NAND Flash
2020 IEEE International Reliability Physics Symposium (IRPS), 2020Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Patrick Breen, Ioannou Nikolas, Gary A TresslerAbstract:3D QLC NAND has recently entered the SSD market offering capacity increase and cost reduction compared to 3D TLC NAND. However, the endurance of QLC NAND is limited. Moreover, due to reduction of the available margin between the programmed threshold Voltage distributions, QLC NAND is more susceptible to bit errors. Read Voltage calibration is a key element of modern NAND flash memory controllers to improve the overall bit-error rate and maintain enterprise level reliability. To reduce the calibration overhead associated with the increased number of pages and Read Voltages in QLC NAND, page grouping is an effective approach. This paper presents open block characterization and Read Voltage calibration results of state-of-the-art 3D QLC NAND. We present experimental measurements of the bit-error characteristics and threshold Voltage distributions based on closed and open block test patterns. We discuss the reliability issues with open blocks in preserving uniform characteristics within a page group at the boundary programmed layer and analyze the performance of different calibration algorithms.
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IRPS - Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory
2019 IEEE International Reliability Physics Symposium (IRPS), 2019Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Roman A Pletka, Sasa Tomic, Patrick Breen, Gary A Tressler, Ioannou Nikolas, Aaron D. Fry, Timothy J. FisherAbstract:3D NAND flash memory has entered dynamically into the space of enterprise server and storage systems, offering significantly higher capacity and better endurance than the latest 2D technology node. Moreover, the advancements in vertical stacking, cell design and program/Read algorithms, have also enabled TLC 3D NAND flash with enterprise-level reliability, thus achieving further increase in capacity and cost-per-bit reduction. This paper presents an in-depth analysis of the bit-error characteristics of state-of-the-art 64-layer 3D TLC NAND flash with a focus on Read-Voltage calibration. We provide experimental measurements of the RBER and threshold Voltage distributions using typical and mixed-mode test patterns of program/erase cycling, retention and Read-disturb. Moreover, we quantify the RBER components attributed to threshold Voltage level overlapping and on-chip 2-step program errors. Finally, we characterize how the optimal Read Voltages change under different device stress and we evaluate calibration schemes with different performance and complexity trade-offs.
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using adaptive Read Voltage thresholds to enhance the reliability of mlc nand flash memory systems
Great Lakes Symposium on VLSI, 2014Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Gary A Tressler, Thomas Mittelholzer, Evangelos Eleftheriou, Charles J Camp, Thomas D Griffin, Andrew D WallsAbstract:NAND Flash memory is not only the ubiquitous storage medium in consumer applications, but has also started to appear in enterprise storage systems as well. MLC and TLC Flash technology made it possible to store multiple bits in the same silicon area as SLC, thus reducing the cost per amount of data stored. However, at current sub-20nm technology nodes, MLC Flash devices fail to provide the levels of raw reliability, mainly cycling endurance, that are required by typical enterprise applications. Advanced signal-processing and coding schemes are needed to improve the Flash bit error rate and thus elevate the device reliability to the desired level. In this paper, we report on the use of adaptive Voltage thresholds in the Read operation of NAND Flash devices. We discuss how the optimal Read Voltage thresholds can be determined, and assess the benefit of adapting the Read Voltage thresholds in terms of cycling endurance, data retention and resilience to Read disturb.
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ACM Great Lakes Symposium on VLSI - Using adaptive Read Voltage thresholds to enhance the reliability of MLC NAND flash memory systems
Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14, 2014Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Gary A Tressler, Thomas Mittelholzer, Evangelos Eleftheriou, Charles J Camp, Thomas D Griffin, Andrew D WallsAbstract:NAND Flash memory is not only the ubiquitous storage medium in consumer applications, but has also started to appear in enterprise storage systems as well. MLC and TLC Flash technology made it possible to store multiple bits in the same silicon area as SLC, thus reducing the cost per amount of data stored. However, at current sub-20nm technology nodes, MLC Flash devices fail to provide the levels of raw reliability, mainly cycling endurance, that are required by typical enterprise applications. Advanced signal-processing and coding schemes are needed to improve the Flash bit error rate and thus elevate the device reliability to the desired level. In this paper, we report on the use of adaptive Voltage thresholds in the Read operation of NAND Flash devices. We discuss how the optimal Read Voltage thresholds can be determined, and assess the benefit of adapting the Read Voltage thresholds in terms of cycling endurance, data retention and resilience to Read disturb.
Thomas Parnell - One of the best experts on this subject based on the ideXlab platform.
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open block characterization and Read Voltage calibration of 3d qlc nand flash
International Reliability Physics Symposium, 2020Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Nikolas Ioannou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Patrick Breen, Gary A TresslerAbstract:3D QLC NAND has recently entered the SSD market offering capacity increase and cost reduction compared to 3D TLC NAND. However, the endurance of QLC NAND is limited. Moreover, due to reduction of the available margin between the programmed threshold Voltage distributions, QLC NAND is more susceptible to bit errors. Read Voltage calibration is a key element of modern NAND flash memory controllers to improve the overall bit-error rate and maintain enterprise level reliability. To reduce the calibration overhead associated with the increased number of pages and Read Voltages in QLC NAND, page grouping is an effective approach. This paper presents open block characterization and Read Voltage calibration results of state-of-the-art 3D QLC NAND. We present experimental measurements of the bit-error characteristics and threshold Voltage distributions based on closed and open block test patterns. We discuss the reliability issues with open blocks in preserving uniform characteristics within a page group at the boundary programmed layer and analyze the performance of different calibration algorithms.
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IRPS - Open Block Characterization and Read Voltage Calibration of 3D QLC NAND Flash
2020 IEEE International Reliability Physics Symposium (IRPS), 2020Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Patrick Breen, Ioannou Nikolas, Gary A TresslerAbstract:3D QLC NAND has recently entered the SSD market offering capacity increase and cost reduction compared to 3D TLC NAND. However, the endurance of QLC NAND is limited. Moreover, due to reduction of the available margin between the programmed threshold Voltage distributions, QLC NAND is more susceptible to bit errors. Read Voltage calibration is a key element of modern NAND flash memory controllers to improve the overall bit-error rate and maintain enterprise level reliability. To reduce the calibration overhead associated with the increased number of pages and Read Voltages in QLC NAND, page grouping is an effective approach. This paper presents open block characterization and Read Voltage calibration results of state-of-the-art 3D QLC NAND. We present experimental measurements of the bit-error characteristics and threshold Voltage distributions based on closed and open block test patterns. We discuss the reliability issues with open blocks in preserving uniform characteristics within a page group at the boundary programmed layer and analyze the performance of different calibration algorithms.
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reliability of 3d nand flash memory with a focus on Read Voltage calibration from a system aspect
Non-Volatile Memory Technology Symposium, 2019Co-Authors: Nikolaos Papandreou, Nikolas Ioannou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Haralampos PozidisAbstract:This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the Read Voltage calibration and its critical role in achieving low error-rates and low latency Read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and Read-disturb from different Read Voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.
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NVMTS - Reliability of 3D NAND flash memory with a focus on Read Voltage calibration from a system aspect
2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 2019Co-Authors: Nikolaos Papandreou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Ioannou Nikolas, Haralampos PozidisAbstract:This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the Read Voltage calibration and its critical role in achieving low error-rates and low latency Read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and Read-disturb from different Read Voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.
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IRPS - Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory
2019 IEEE International Reliability Physics Symposium (IRPS), 2019Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Roman A Pletka, Sasa Tomic, Patrick Breen, Gary A Tressler, Ioannou Nikolas, Aaron D. Fry, Timothy J. FisherAbstract:3D NAND flash memory has entered dynamically into the space of enterprise server and storage systems, offering significantly higher capacity and better endurance than the latest 2D technology node. Moreover, the advancements in vertical stacking, cell design and program/Read algorithms, have also enabled TLC 3D NAND flash with enterprise-level reliability, thus achieving further increase in capacity and cost-per-bit reduction. This paper presents an in-depth analysis of the bit-error characteristics of state-of-the-art 64-layer 3D TLC NAND flash with a focus on Read-Voltage calibration. We provide experimental measurements of the RBER and threshold Voltage distributions using typical and mixed-mode test patterns of program/erase cycling, retention and Read-disturb. Moreover, we quantify the RBER components attributed to threshold Voltage level overlapping and on-chip 2-step program errors. Finally, we characterize how the optimal Read Voltages change under different device stress and we evaluate calibration schemes with different performance and complexity trade-offs.
Roman A Pletka - One of the best experts on this subject based on the ideXlab platform.
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open block characterization and Read Voltage calibration of 3d qlc nand flash
International Reliability Physics Symposium, 2020Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Nikolas Ioannou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Patrick Breen, Gary A TresslerAbstract:3D QLC NAND has recently entered the SSD market offering capacity increase and cost reduction compared to 3D TLC NAND. However, the endurance of QLC NAND is limited. Moreover, due to reduction of the available margin between the programmed threshold Voltage distributions, QLC NAND is more susceptible to bit errors. Read Voltage calibration is a key element of modern NAND flash memory controllers to improve the overall bit-error rate and maintain enterprise level reliability. To reduce the calibration overhead associated with the increased number of pages and Read Voltages in QLC NAND, page grouping is an effective approach. This paper presents open block characterization and Read Voltage calibration results of state-of-the-art 3D QLC NAND. We present experimental measurements of the bit-error characteristics and threshold Voltage distributions based on closed and open block test patterns. We discuss the reliability issues with open blocks in preserving uniform characteristics within a page group at the boundary programmed layer and analyze the performance of different calibration algorithms.
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IRPS - Open Block Characterization and Read Voltage Calibration of 3D QLC NAND Flash
2020 IEEE International Reliability Physics Symposium (IRPS), 2020Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Patrick Breen, Ioannou Nikolas, Gary A TresslerAbstract:3D QLC NAND has recently entered the SSD market offering capacity increase and cost reduction compared to 3D TLC NAND. However, the endurance of QLC NAND is limited. Moreover, due to reduction of the available margin between the programmed threshold Voltage distributions, QLC NAND is more susceptible to bit errors. Read Voltage calibration is a key element of modern NAND flash memory controllers to improve the overall bit-error rate and maintain enterprise level reliability. To reduce the calibration overhead associated with the increased number of pages and Read Voltages in QLC NAND, page grouping is an effective approach. This paper presents open block characterization and Read Voltage calibration results of state-of-the-art 3D QLC NAND. We present experimental measurements of the bit-error characteristics and threshold Voltage distributions based on closed and open block test patterns. We discuss the reliability issues with open blocks in preserving uniform characteristics within a page group at the boundary programmed layer and analyze the performance of different calibration algorithms.
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reliability of 3d nand flash memory with a focus on Read Voltage calibration from a system aspect
Non-Volatile Memory Technology Symposium, 2019Co-Authors: Nikolaos Papandreou, Nikolas Ioannou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Haralampos PozidisAbstract:This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the Read Voltage calibration and its critical role in achieving low error-rates and low latency Read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and Read-disturb from different Read Voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.
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NVMTS - Reliability of 3D NAND flash memory with a focus on Read Voltage calibration from a system aspect
2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 2019Co-Authors: Nikolaos Papandreou, Thomas Parnell, Roman A Pletka, Milos Stanisavljevic, Radu Stoica, Sasa Tomic, Ioannou Nikolas, Haralampos PozidisAbstract:This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the Read Voltage calibration and its critical role in achieving low error-rates and low latency Read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and Read-disturb from different Read Voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.
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IRPS - Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory
2019 IEEE International Reliability Physics Symposium (IRPS), 2019Co-Authors: Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Roman A Pletka, Sasa Tomic, Patrick Breen, Gary A Tressler, Ioannou Nikolas, Aaron D. Fry, Timothy J. FisherAbstract:3D NAND flash memory has entered dynamically into the space of enterprise server and storage systems, offering significantly higher capacity and better endurance than the latest 2D technology node. Moreover, the advancements in vertical stacking, cell design and program/Read algorithms, have also enabled TLC 3D NAND flash with enterprise-level reliability, thus achieving further increase in capacity and cost-per-bit reduction. This paper presents an in-depth analysis of the bit-error characteristics of state-of-the-art 64-layer 3D TLC NAND flash with a focus on Read-Voltage calibration. We provide experimental measurements of the RBER and threshold Voltage distributions using typical and mixed-mode test patterns of program/erase cycling, retention and Read-disturb. Moreover, we quantify the RBER components attributed to threshold Voltage level overlapping and on-chip 2-step program errors. Finally, we characterize how the optimal Read Voltages change under different device stress and we evaluate calibration schemes with different performance and complexity trade-offs.
