The Experts below are selected from a list of 555 Experts worldwide ranked by ideXlab platform
Dirk Timmermann - One of the best experts on this subject based on the ideXlab platform.
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Dynamic Single-rail Self-timed Logic Structures for Power Efficient Synchronous Pipelined Designs
2015Co-Authors: Frank Grassert, Dirk TimmermannAbstract:The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combine improvements on algorithm and logic level. To reduce the power consumption of dynamic logic, a method for using single-rail structures is presented including a new scheme to realize inverting logic functions. It is shown that such structure is most efficient when Redundant number systems are utilized. These self-timed logic is integrated in a global clock system using the Asynchronous Chain True Single Phase Clock (AC-TSPC) logic resulting in a latch-free structure. Comparisons with other logic styles show the achievement potential. First simulations for a horizontal Redundant Adder slice show area and power savings of 40 % and 30 % compared to complementary Domino logic
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Single-Rail Self-timed Logic Circuits in Synchronous Designs
2002Co-Authors: Frank Grassert, Dirk TimmermannAbstract:This paper presents a self-timed scheme for dynamic single-rail logic integrated in a single phase clock design. A generalized completion detection for generation of self-timed signals from single-rail gates is described and we show a novel application of the redundancy of a SD-Adder to ease the self-timed signal generation. Further we discuss an universal evaluation scheme to overcome the problem of only non-inverting functions with dynamic single-rail gates. The presented SD-Adder was integrated in a synchronous scheme and combines the advantages of simple synthesis and clock distribution for synchronous designs with fastest evaluation. Self-timed schemes result in fastest latch-free structures and robustness against clock-skew. Further the single-rail scheme on gate-level yields lower power consumption and smaller circuits. The use of inverting and non-inverting single-rail gates makes the synthesis close to standard synthesis. Simulations for the Redundant Adder design show area and power savings of 40% and 30% compared to complementary DOMINO logic structure
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Scalable Counter Architecture for a Pre-loadable ... Pre-scaler in TSPC
2001Co-Authors: Andreas Wassatsch, Dirk TimmermannAbstract:In this paper we describe an approach for using the true single phase clock (TSPC) circuit style for the implementation of a scalable, pre-loadable pre-scaler. By utilization of a signed digit (SD) based Redundant Adder cell the execution of the necessary addition operation can be performed in only one clock cycle, independent from the length of the applied operators. The development process for this SD-Adder cell by reorganization and partitioning of the necessary logic in connection with an enhancement of the TSPC circuit style will be discussed. The determination of the zero-crossing is also as far as possible independent from the word length by deployment of a TSPC OR-cell. Furthermore, a reference implementation of a 8-digit pre-scaler circuit operating at 1GHz with a 5V power supply in a #:#m AMS CMOS process will be presented. The goal of this paper is to develop a strategy for the implementation of pre-scaler circuits based on Redundant arithmetic, which can operate at high frequencies. The comparison with the results of other implementations illustrate the advantages of our approach. 1
Ghassem Jaberipur - One of the best experts on this subject based on the ideXlab platform.
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An efficient universal addition scheme for all hybrid-Redundant representations with weighted bit-set encoding
2006Co-Authors: Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi, Prof Behrooz ParhamiAbstract:Redundant and hybrid-Redundant number representations are used extensively to speed up arithmetic operations within general-purpose and special-purpose digital systems, with the latter (containing both Redundant and nonRedundant digits) offering cost advantages over fully Redundant systems. We use weighted bit-set (WBS) encoding as a paradigm for uniform treatment of five previously studied variants of hybrid-Redundant systems. We then extend the class of hybrid Redundant numbers to coincide with the entire set of canonical WBS numbers by allowing an arbitrary nonRedundant position, heretofore restricted to ordinary bits (posibits), to hold a negatively weighted bit (negabit). This flexibility leads to interesting and useful symmetric variants of hybrid-Redundant representations. We provide a high-level circuit design, based solely on binary full-Adders, for a constant-time universal hybrid-Redundant Adder capable of producing a canonical WBS-encoded sum of two canonical WBS (or extended hybrid) numbers. This is made possible by the use of conventional binary full-Adders for reducing any collection of three posibits and negabits, where negabits use an inverted encoding. We compare our Adder to previous designs, showing advantages in speed, cost, and regularity. Furthermore we explore representationally closed addition schemes, holding the benefit of greater regularity an
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An Efficient Universal Addition Scheme for all HybridRedundant Representations with Weighted Bit-Set Encoding
2006Co-Authors: Ghassem JaberipurAbstract:Abstract. Redundant and hybrid-Redundant number representations are used extensively to speed up arithmetic operations within general-purpose and special-purpose digital systems, with the latter (containing both Redundant and nonRedundant digits) offering cost advantages over fully Redundant systems. We use weighted bit-set (WBS) encoding as a paradigm for uniform treatment of five previously studied variants of hybrid-Redundant systems. We then extend the class of hybrid-Redundant numbers to coincide with the entire set of canonical WBS numbers by allowing an arbitrary nonRedundant position, heretofore restricted to ordinary bits (posibits), to hold a negatively weighted bit (negabit). This flexibility leads to interesting and useful symmetric variants of hybrid-Redundant representations. We provide a high-level circuit design, based solely on binary full-Adders, for a constant-time universal hybrid-Redundant Adder capable of producing a canonical WBS-encoded sum of two canonical WBS (or extended hybrid) numbers. This is made possible by the use of conventional binary full-Adders for reducing any collection of three posibits and negabits, where negabits use an inverted encoding. We compare our Adder to previous designs, showing advantages in speed, cost, and regularity. Furthermore we explore representationally closed addition schemes, holding the benefit of greater regularity and reusability, and provide high-level representationally closed designs for all the previously studied variants of hybrid redundancy and for the new symmetric variants introduced here. Finally, we present a new functionality for a conventional (4; 2) compressor in combining an
Frank Grassert - One of the best experts on this subject based on the ideXlab platform.
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Dynamic Single-rail Self-timed Logic Structures for Power Efficient Synchronous Pipelined Designs
2015Co-Authors: Frank Grassert, Dirk TimmermannAbstract:The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combine improvements on algorithm and logic level. To reduce the power consumption of dynamic logic, a method for using single-rail structures is presented including a new scheme to realize inverting logic functions. It is shown that such structure is most efficient when Redundant number systems are utilized. These self-timed logic is integrated in a global clock system using the Asynchronous Chain True Single Phase Clock (AC-TSPC) logic resulting in a latch-free structure. Comparisons with other logic styles show the achievement potential. First simulations for a horizontal Redundant Adder slice show area and power savings of 40 % and 30 % compared to complementary Domino logic
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Single-Rail Self-timed Logic Circuits in Synchronous Designs
2002Co-Authors: Frank Grassert, Dirk TimmermannAbstract:This paper presents a self-timed scheme for dynamic single-rail logic integrated in a single phase clock design. A generalized completion detection for generation of self-timed signals from single-rail gates is described and we show a novel application of the redundancy of a SD-Adder to ease the self-timed signal generation. Further we discuss an universal evaluation scheme to overcome the problem of only non-inverting functions with dynamic single-rail gates. The presented SD-Adder was integrated in a synchronous scheme and combines the advantages of simple synthesis and clock distribution for synchronous designs with fastest evaluation. Self-timed schemes result in fastest latch-free structures and robustness against clock-skew. Further the single-rail scheme on gate-level yields lower power consumption and smaller circuits. The use of inverting and non-inverting single-rail gates makes the synthesis close to standard synthesis. Simulations for the Redundant Adder design show area and power savings of 40% and 30% compared to complementary DOMINO logic structure
F Pourbigharaz - One of the best experts on this subject based on the ideXlab platform.
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a signed digit architecture for residue to binary transformation
IEEE Transactions on Computers, 1997Co-Authors: F PourbigharazAbstract:A residue to binary converter architecture based on the Chinese Remainder Theorem (CRT) is presented. This is achieved by introducing a general moduli set S/sup k/ S/sup k/={2/sup m/-1, 2/sup 2om/+1, 2/sup 21m/+1, 2/sup 22m/+1,....,2/sup 22km/+1} for Residue Number System (RNS) applications. Residue to binary converter architectures based on moduli sets S/sup o/={2/sup m/-1, 2/sup m/+1} and S/sup 1/=(2/sup m/-1, 2/sup m/+1, 2/sup 2m/+1) are developed. The conversion procedure is performed in the following three levels: residue to signed-digit, signed-digit to binary, end-around carry addition/subtraction. In the first level of operation, the signed-digit representation of the CRT equation is realized by using Redundant Adder/subtracter blocks. Here, the necessary embedded multiplications are replaced by simple shift-left operations and the carry propagation is totally eliminated. In the second level, the Redundant representation of CRT is directly converted to binary format. Finally, an end-around carry (EAC) addition/subtraction is performed to obtain the result at the third level of operation. The proposed architectures are simple, fast, free of memory blocks and module Adders.
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intermediate signed digit stage to perform residue to binary transformations based on crt
International Symposium on Circuits and Systems, 1994Co-Authors: F Pourbigharaz, H M YassineAbstract:A residue to binary converter architecture based on the Chinese Remainder Theorem (CRT) is presented. The conversion from residue to binary is performed in three levels: residue to signed-digit; signed-digit to binary; end-around carry Adder/subtracter. By choosing the residue number systems based on (2/sup m/-1, 2/sup m/+1) or (2/sup m/-1, 2/sup m/+1, 2/sup 2m/+1) moduli sets, the necessary multiplication operations embedded within the CRT can be replaced by simple shift left operations. The CRT equation is realized by using Redundant Adder/subtracter blocks in the first level and the carry propagation is totally eliminated. The second level of operation converts the Redundant form of CRT to the binary representation. The proposed architecture is free of modulo-M Adders. This is achieved by using an end-around carry propagate Adder/subtracter in the third level. The two moduli converter was designed and simulated on Cadence. >
Prof Behrooz Parhami - One of the best experts on this subject based on the ideXlab platform.
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An efficient universal addition scheme for all hybrid-Redundant representations with weighted bit-set encoding
2006Co-Authors: Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi, Prof Behrooz ParhamiAbstract:Redundant and hybrid-Redundant number representations are used extensively to speed up arithmetic operations within general-purpose and special-purpose digital systems, with the latter (containing both Redundant and nonRedundant digits) offering cost advantages over fully Redundant systems. We use weighted bit-set (WBS) encoding as a paradigm for uniform treatment of five previously studied variants of hybrid-Redundant systems. We then extend the class of hybrid Redundant numbers to coincide with the entire set of canonical WBS numbers by allowing an arbitrary nonRedundant position, heretofore restricted to ordinary bits (posibits), to hold a negatively weighted bit (negabit). This flexibility leads to interesting and useful symmetric variants of hybrid-Redundant representations. We provide a high-level circuit design, based solely on binary full-Adders, for a constant-time universal hybrid-Redundant Adder capable of producing a canonical WBS-encoded sum of two canonical WBS (or extended hybrid) numbers. This is made possible by the use of conventional binary full-Adders for reducing any collection of three posibits and negabits, where negabits use an inverted encoding. We compare our Adder to previous designs, showing advantages in speed, cost, and regularity. Furthermore we explore representationally closed addition schemes, holding the benefit of greater regularity an
