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Deloge Matthieu - One of the best experts on this subject based on the ideXlab platform.
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Contribution à l'analyse des mécanismes de claquage d’oxyde ultra mince et applications aux mémoires antifusibles en technologies avancées
2011Co-Authors: Deloge MatthieuAbstract:Les mémoires non-volatiles programmables une fois sont en plein essor dans le monde de l’électronique embarquée. La traçabilité, la configuration ou encore la réparation de systèmes sur puce avancés font partis des applications adressées par ce type de mémoire. Plus particulièrement, la technologie antifusible présente des propriétés de sécurité autorisant le stockage d’information sensible.Ce travail de thèse est orienté vers la compréhension des mécanismes de claquage d’oxydes minces sollicités pour la programmation des cellules antifusibles ainsi que l’intégration au niveau système de moyens de détections. Une première étape fut d’étudier les phénomènes de claquage de diélectrique type SiO2 et à haute permittivité sous l’application d’un fort champ ́électrique. Des techniques de mesures dédiées ont été développées afin de réaliser des caractérisations dans les conditions de programmation des mémoires antifusible sollicitant des temps au claquage inférieurs à la micro-seconde. Ces mesures ont ensuite permis l’étude statistique du claquage des diélectriques ainsi que la modélisation sous de hautes tensions ; hors des gammes étudiées traditionnellement dans le domaine de la fiabilité. Le modèle proposé permet l’optimisation des dimensions d’une cellule élémentaire en fonction d’un temps au claquage défini au préalable. Un mécanisme inattendu occasionnant un sur courant substrat a également été mis en évidence pendant la phase de programmation. L’étude de ce phénomène a été réalisée par des caractérisations électriques et des simulations afin de conclure sur l’hypothèse d’un déclenchement d’un transistor bipolaire parasite de type PNP dans la cellule antifusible. L’impact des conditions de programmation sur le courant de lecture mesuré sous une basse tension a également été analysé. Des structures de tests analogiques dédiés ont été conçues afin de contrôler l’amplitude du courant de programmation. Le contrôle du temps de programmation est quant à lui accompli par un système de détection de courant et de temporisation. Finalement, ces solutions sont validées par un démonstrateur d’une capacité de 1-kb conçu et fabriqué sur une technologie CMOS standard avancée 32nm.Non-volatile one-time programmable memories are gaining an ever growing interest in embedded electronics. Chip ID, chip configuration or system repairing are among the numerous applications addressed by this type of semiconductor memories. In addition, the antifuse technology enables the storage of secured information with respect to cryptography or else. The thesis focuses on the understanding of ultrathin gate-oxide breakdown physics that is involved in the programming of antifuse bitcells. The integration of advanced programming and detection schemes is also tackled in this thesis. The breakdown mechanisms in the dielectric material SiO2 and high-K under a high electric field were studied. Dedicated experimental setups were needed in order to perform the characterization of antifuse bitcells under the conditions define in memory product. Typical time-to-breakdown values shorter than a micro second were identified. The latter measurements allowed the statistical study of dielectric breakdown and the modeling in a high voltage range, i.e. beyond the conventional range studied in reliability. The model presented in this PhD thesis enables the optimization of the antifuse bitcell sizes according to a targeted mean time-to- breakdown value. A particular mechanism leading to a high bulk current overshoot occuring during the programming operation was highlighted. The study of this phenomenon was achieved using electrical characterizations and simulations. The triggering of a parasitic P-N-P bipolar transistor localized in the antifuse bitcell appeared as a Relevant Hypothesis. The analysis of the impact of the programming conditions on the resulting read current measured under a low voltage was performed using analog test structures. The amplitude of the programming current was controlled in an augmented antifuse bitcell. The programming time is controlled by a programming detection system and a delay. Finally, these solutions are to be validated using a 1-kb demonstrator yet designed and fabricated in a logic 32-nm CMOS process
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Contribution à l'analyse des mécanismes de claquage d oxyde ultra mince et applications aux mémoires antifusibles en technologies avancées
2011Co-Authors: Deloge Matthieu, Allard BrunoAbstract:Les mémoires non-volatiles programmables une fois sont en plein essor dans le monde de l électronique embarquée. La traçabilité, la configuration ou encore la réparation de systèmes sur puce avancés font partis des applications adressées par ce type de mémoire. Plus particulièrement, la technologie antifusible présente des propriétés de sécurité autorisant le stockage d information sensible.Ce travail de thèse est orienté vers la compréhension des mécanismes de claquage d oxydes minces sollicités pour la programmation des cellules antifusibles ainsi que l intégration au niveau système de moyens de détections. Une première étape fut d étudier les phénomènes de claquage de diélectrique type SiO2 et à haute permittivité sous l application d un fort champ électrique. Des techniques de mesures dédiées ont été développées afin de réaliser des caractérisations dans les conditions de programmation des mémoires antifusible sollicitant des temps au claquage inférieurs à la micro-seconde. Ces mesures ont ensuite permis l étude statistique du claquage des diélectriques ainsi que la modélisation sous de hautes tensions ; hors des gammes étudiées traditionnellement dans le domaine de la fiabilité. Le modèle proposé permet l optimisation des dimensions d une cellule élémentaire en fonction d un temps au claquage défini au préalable. Un mécanisme inattendu occasionnant un sur courant substrat a également été mis en évidence pendant la phase de programmation. L étude de ce phénomène a été réalisée par des caractérisations électriques et des simulations afin de conclure sur l hypothèse d un déclenchement d un transistor bipolaire parasite de type PNP dans la cellule antifusible. L impact des conditions de programmation sur le courant de lecture mesuré sous une basse tension a également été analysé. Des structures de tests analogiques dédiés ont été conçues afin de contrôler l amplitude du courant de programmation. Le contrôle du temps de programmation est quant à lui accompli par un système de détection de courant et de temporisation. Finalement, ces solutions sont validées par un démonstrateur d une capacité de 1-kb conçu et fabriqué sur une technologie CMOS standard avancée 32nm.Non-volatile one-time programmable memories are gaining an ever growing interest in embedded electronics. Chip ID, chip configuration or system repairing are among the numerous applications addressed by this type of semiconductor memories. In addition, the antifuse technology enables the storage of secured information with respect to cryptography or else. The thesis focuses on the understanding of ultrathin gate-oxide breakdown physics that is involved in the programming of antifuse bitcells. The integration of advanced programming and detection schemes is also tackled in this thesis. The breakdown mechanisms in the dielectric material SiO2 and high-K under a high electric field were studied. Dedicated experimental setups were needed in order to perform the characterization of antifuse bitcells under the conditions define in memory product. Typical time-to-breakdown values shorter than a micro second were identified. The latter measurements allowed the statistical study of dielectric breakdown and the modeling in a high voltage range, i.e. beyond the conventional range studied in reliability. The model presented in this PhD thesis enables the optimization of the antifuse bitcell sizes according to a targeted mean time-to- breakdown value. A particular mechanism leading to a high bulk current overshoot occuring during the programming operation was highlighted. The study of this phenomenon was achieved using electrical characterizations and simulations. The triggering of a parasitic P-N-P bipolar transistor localized in the antifuse bitcell appeared as a Relevant Hypothesis. The analysis of the impact of the programming conditions on the resulting read current measured under a low voltage was performed using analog test structures. The amplitude of the programming current was controlled in an augmented antifuse bitcell. The programming time is controlled by a programming detection system and a delay. Finally, these solutions are to be validated using a 1-kb demonstrator yet designed and fabricated in a logic 32-nm CMOS process.VILLEURBANNE-DOC'INSA LYON (692662301) / SudocVILLEURBANNE-DOC'INSA-Bib. elec. (692669901) / SudocSudocFranceF
Spyros Matsoukas - One of the best experts on this subject based on the ideXlab platform.
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a re ranker scheme for integrating large scale nlu models
arXiv: Computation and Language, 2018Co-Authors: Rahul Gupta, Shankar Ananthakrishnan, Spyros MatsoukasAbstract:Large scale Natural Language Understanding (NLU) systems are typically trained on large quantities of data, requiring a fast and scalable training strategy. A typical design for NLU systems consists of domain-level NLU modules (domain classifier, intent classifier and named entity recognizer). Hypotheses (NLU interpretations consisting of various intent+slot combinations) from these domain specific modules are typically aggregated with another downstream component. The re-ranker integrates outputs from domain-level recognizers, returning a scored list of cross domain hypotheses. An ideal re-ranker will exhibit the following two properties: (a) it should prefer the most Relevant Hypothesis for the given input as the top Hypothesis and, (b) the interpretation scores corresponding to each Hypothesis produced by the re-ranker should be calibrated. Calibration allows the final NLU interpretation score to be comparable across domains. We propose a novel re-ranker strategy that addresses these aspects, while also maintaining domain specific modularity. We design optimization loss functions for such a modularized re-ranker and present results on decreasing the top Hypothesis error rate as well as maintaining the model calibration. We also experiment with an extension involving training the domain specific re-rankers on datasets curated independently by each domain to allow further asynchronization. %The proposed re-ranker design showcases the following: (i) improved NLU performance over an unweighted aggregation strategy, (ii) cross-domain calibrated performance and, (iii) support for use cases involving training each re-ranker on datasets curated by each domain independently.
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A Re-Ranker Scheme For Integrating Large Scale NLU Models
2018 IEEE Spoken Language Technology Workshop (SLT), 2018Co-Authors: Rahul Gupta, Shankar Ananthakrishnan, Spyros MatsoukasAbstract:Large scale Natural Language Understanding (NLU) systems are typically trained on large quantities of data, requiring a fast and scalable training strategy. A typical design for NLU systems consists of domain-level NLU modules (domain classifier, intent classifier and named entity recognizer). Hypotheses (NLU interpretations consisting of various intent+slot combinations) from these domain specific modules are typically aggregated with another downstream component. The re-ranker integrates outputs from domain-level recognizers, returning a scored list of cross domain hypotheses. An ideal re-ranker will exhibit the following two properties: (a) it should prefer the most Relevant Hypothesis for the given input as the top Hypothesis and, (b) the interpretation scores corresponding to each Hypothesis produced by the re-ranker should be calibrated. Calibration allows the final NLU interpretation score to be comparable across domains. We propose a novel re-ranker strategy that addresses these aspects, while also maintaining domain specific modularity. We design optimization loss functions for such a modularized re-ranker and present results on decreasing the top Hypothesis error rate as well as maintaining the model calibration. We also experiment with an extension involving training the domain specific re-rankers on datasets curated independently by each domain to allow further asynchronization.
Allard Bruno - One of the best experts on this subject based on the ideXlab platform.
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Contribution à l'analyse des mécanismes de claquage d oxyde ultra mince et applications aux mémoires antifusibles en technologies avancées
2011Co-Authors: Deloge Matthieu, Allard BrunoAbstract:Les mémoires non-volatiles programmables une fois sont en plein essor dans le monde de l électronique embarquée. La traçabilité, la configuration ou encore la réparation de systèmes sur puce avancés font partis des applications adressées par ce type de mémoire. Plus particulièrement, la technologie antifusible présente des propriétés de sécurité autorisant le stockage d information sensible.Ce travail de thèse est orienté vers la compréhension des mécanismes de claquage d oxydes minces sollicités pour la programmation des cellules antifusibles ainsi que l intégration au niveau système de moyens de détections. Une première étape fut d étudier les phénomènes de claquage de diélectrique type SiO2 et à haute permittivité sous l application d un fort champ électrique. Des techniques de mesures dédiées ont été développées afin de réaliser des caractérisations dans les conditions de programmation des mémoires antifusible sollicitant des temps au claquage inférieurs à la micro-seconde. Ces mesures ont ensuite permis l étude statistique du claquage des diélectriques ainsi que la modélisation sous de hautes tensions ; hors des gammes étudiées traditionnellement dans le domaine de la fiabilité. Le modèle proposé permet l optimisation des dimensions d une cellule élémentaire en fonction d un temps au claquage défini au préalable. Un mécanisme inattendu occasionnant un sur courant substrat a également été mis en évidence pendant la phase de programmation. L étude de ce phénomène a été réalisée par des caractérisations électriques et des simulations afin de conclure sur l hypothèse d un déclenchement d un transistor bipolaire parasite de type PNP dans la cellule antifusible. L impact des conditions de programmation sur le courant de lecture mesuré sous une basse tension a également été analysé. Des structures de tests analogiques dédiés ont été conçues afin de contrôler l amplitude du courant de programmation. Le contrôle du temps de programmation est quant à lui accompli par un système de détection de courant et de temporisation. Finalement, ces solutions sont validées par un démonstrateur d une capacité de 1-kb conçu et fabriqué sur une technologie CMOS standard avancée 32nm.Non-volatile one-time programmable memories are gaining an ever growing interest in embedded electronics. Chip ID, chip configuration or system repairing are among the numerous applications addressed by this type of semiconductor memories. In addition, the antifuse technology enables the storage of secured information with respect to cryptography or else. The thesis focuses on the understanding of ultrathin gate-oxide breakdown physics that is involved in the programming of antifuse bitcells. The integration of advanced programming and detection schemes is also tackled in this thesis. The breakdown mechanisms in the dielectric material SiO2 and high-K under a high electric field were studied. Dedicated experimental setups were needed in order to perform the characterization of antifuse bitcells under the conditions define in memory product. Typical time-to-breakdown values shorter than a micro second were identified. The latter measurements allowed the statistical study of dielectric breakdown and the modeling in a high voltage range, i.e. beyond the conventional range studied in reliability. The model presented in this PhD thesis enables the optimization of the antifuse bitcell sizes according to a targeted mean time-to- breakdown value. A particular mechanism leading to a high bulk current overshoot occuring during the programming operation was highlighted. The study of this phenomenon was achieved using electrical characterizations and simulations. The triggering of a parasitic P-N-P bipolar transistor localized in the antifuse bitcell appeared as a Relevant Hypothesis. The analysis of the impact of the programming conditions on the resulting read current measured under a low voltage was performed using analog test structures. The amplitude of the programming current was controlled in an augmented antifuse bitcell. The programming time is controlled by a programming detection system and a delay. Finally, these solutions are to be validated using a 1-kb demonstrator yet designed and fabricated in a logic 32-nm CMOS process.VILLEURBANNE-DOC'INSA LYON (692662301) / SudocVILLEURBANNE-DOC'INSA-Bib. elec. (692669901) / SudocSudocFranceF
Rahul Gupta - One of the best experts on this subject based on the ideXlab platform.
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a re ranker scheme for integrating large scale nlu models
arXiv: Computation and Language, 2018Co-Authors: Rahul Gupta, Shankar Ananthakrishnan, Spyros MatsoukasAbstract:Large scale Natural Language Understanding (NLU) systems are typically trained on large quantities of data, requiring a fast and scalable training strategy. A typical design for NLU systems consists of domain-level NLU modules (domain classifier, intent classifier and named entity recognizer). Hypotheses (NLU interpretations consisting of various intent+slot combinations) from these domain specific modules are typically aggregated with another downstream component. The re-ranker integrates outputs from domain-level recognizers, returning a scored list of cross domain hypotheses. An ideal re-ranker will exhibit the following two properties: (a) it should prefer the most Relevant Hypothesis for the given input as the top Hypothesis and, (b) the interpretation scores corresponding to each Hypothesis produced by the re-ranker should be calibrated. Calibration allows the final NLU interpretation score to be comparable across domains. We propose a novel re-ranker strategy that addresses these aspects, while also maintaining domain specific modularity. We design optimization loss functions for such a modularized re-ranker and present results on decreasing the top Hypothesis error rate as well as maintaining the model calibration. We also experiment with an extension involving training the domain specific re-rankers on datasets curated independently by each domain to allow further asynchronization. %The proposed re-ranker design showcases the following: (i) improved NLU performance over an unweighted aggregation strategy, (ii) cross-domain calibrated performance and, (iii) support for use cases involving training each re-ranker on datasets curated by each domain independently.
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A Re-Ranker Scheme For Integrating Large Scale NLU Models
2018 IEEE Spoken Language Technology Workshop (SLT), 2018Co-Authors: Rahul Gupta, Shankar Ananthakrishnan, Spyros MatsoukasAbstract:Large scale Natural Language Understanding (NLU) systems are typically trained on large quantities of data, requiring a fast and scalable training strategy. A typical design for NLU systems consists of domain-level NLU modules (domain classifier, intent classifier and named entity recognizer). Hypotheses (NLU interpretations consisting of various intent+slot combinations) from these domain specific modules are typically aggregated with another downstream component. The re-ranker integrates outputs from domain-level recognizers, returning a scored list of cross domain hypotheses. An ideal re-ranker will exhibit the following two properties: (a) it should prefer the most Relevant Hypothesis for the given input as the top Hypothesis and, (b) the interpretation scores corresponding to each Hypothesis produced by the re-ranker should be calibrated. Calibration allows the final NLU interpretation score to be comparable across domains. We propose a novel re-ranker strategy that addresses these aspects, while also maintaining domain specific modularity. We design optimization loss functions for such a modularized re-ranker and present results on decreasing the top Hypothesis error rate as well as maintaining the model calibration. We also experiment with an extension involving training the domain specific re-rankers on datasets curated independently by each domain to allow further asynchronization.
Ramesh Narayan - One of the best experts on this subject based on the ideXlab platform.
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density jump as a function of magnetic field strength for parallel collisionless shocks in pair plasmas
arXiv: Plasma Physics, 2018Co-Authors: Antoine Bret, Ramesh NarayanAbstract:Collisionless shocks follow the Rankine-Hugoniot jump conditions to a good approximation. However, for a shock propagating parallel to a magnetic field, magnetohydrodynamics states that the shock properties are independent of the field strength, whereas recent Particle-in-Cell simulations reveal a significant departure from magnetohydrodynamics behavior for such shocks in the collisionless regime. This departure is found to be caused by a field-driven anisotropy in the downstream pressure, but the functional dependence of this anisotropy on the field strength is yet to be determined. Here, we present a non-relativistic model of the plasma evolution through the shock front, allowing for a derivation of the downstream anisotropy in terms of the field strength. Our scenario assumes double adiabatic evolution of a pair plasma through the shock front. As a result, the perpendicular temperature is conserved. If the resulting downstream is firehose stable, then the plasma remains in this state. If unstable, it migrates towards the firehose stability threshold. In both cases, the conservation equations, together with the Relevant Hypothesis made on the temperature, allows a full determination of the downstream anisotropy in terms of the field strength.