The Experts below are selected from a list of 54 Experts worldwide ranked by ideXlab platform
J. Hicks - One of the best experts on this subject based on the ideXlab platform.
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microprocessor Reliability performance as a function of die location for a 0 25 spl mu five layer metal cmos logic process
International Reliability Physics Symposium, 1999Co-Authors: W.c. Riordan, R. Miller, J M Sherman, J. HicksAbstract:In this paper, we present the results of multiple correlations between Reliability (infant mortality and other Reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with Reliability Defect density proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse Reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for Reliability failures.
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Reliability versus yield and die location in advanced VLSI
Microelectronics Reliability, 1999Co-Authors: W.c. Riordan, R. Miller, J. HicksAbstract:Abstract The results of multiple correlations between Reliability and yield on a die level basis are presented for an advanced microprocessors fabricated using a 0.25μ, five layer metal CMOS logic process. Traceability information was programmed into each unit; investigated were infant mortality of edge die versus center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn in failures. The model that Reliability Defect density is proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. Because the traceability information was part of the standard manufacturing flow this analysis was performed using very large, 1 million unit sample sizes.
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Microprocessor Reliability performance as a function of die location for a 0.25 /spl mu/, five layer metal CMOS logic process
1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296), 1Co-Authors: W.c. Riordan, R. Miller, J M Sherman, J. HicksAbstract:In this paper, we present the results of multiple correlations between Reliability (infant mortality and other Reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with Reliability Defect density proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse Reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for Reliability failures.
W.c. Riordan - One of the best experts on this subject based on the ideXlab platform.
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microprocessor Reliability performance as a function of die location for a 0 25 spl mu five layer metal cmos logic process
International Reliability Physics Symposium, 1999Co-Authors: W.c. Riordan, R. Miller, J M Sherman, J. HicksAbstract:In this paper, we present the results of multiple correlations between Reliability (infant mortality and other Reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with Reliability Defect density proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse Reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for Reliability failures.
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Reliability versus yield and die location in advanced VLSI
Microelectronics Reliability, 1999Co-Authors: W.c. Riordan, R. Miller, J. HicksAbstract:Abstract The results of multiple correlations between Reliability and yield on a die level basis are presented for an advanced microprocessors fabricated using a 0.25μ, five layer metal CMOS logic process. Traceability information was programmed into each unit; investigated were infant mortality of edge die versus center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn in failures. The model that Reliability Defect density is proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. Because the traceability information was part of the standard manufacturing flow this analysis was performed using very large, 1 million unit sample sizes.
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Microprocessor Reliability performance as a function of die location for a 0.25 /spl mu/, five layer metal CMOS logic process
1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296), 1Co-Authors: W.c. Riordan, R. Miller, J M Sherman, J. HicksAbstract:In this paper, we present the results of multiple correlations between Reliability (infant mortality and other Reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with Reliability Defect density proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse Reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for Reliability failures.
R. Miller - One of the best experts on this subject based on the ideXlab platform.
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microprocessor Reliability performance as a function of die location for a 0 25 spl mu five layer metal cmos logic process
International Reliability Physics Symposium, 1999Co-Authors: W.c. Riordan, R. Miller, J M Sherman, J. HicksAbstract:In this paper, we present the results of multiple correlations between Reliability (infant mortality and other Reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with Reliability Defect density proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse Reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for Reliability failures.
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Reliability versus yield and die location in advanced VLSI
Microelectronics Reliability, 1999Co-Authors: W.c. Riordan, R. Miller, J. HicksAbstract:Abstract The results of multiple correlations between Reliability and yield on a die level basis are presented for an advanced microprocessors fabricated using a 0.25μ, five layer metal CMOS logic process. Traceability information was programmed into each unit; investigated were infant mortality of edge die versus center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn in failures. The model that Reliability Defect density is proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. Because the traceability information was part of the standard manufacturing flow this analysis was performed using very large, 1 million unit sample sizes.
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Microprocessor Reliability performance as a function of die location for a 0.25 /spl mu/, five layer metal CMOS logic process
1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296), 1Co-Authors: W.c. Riordan, R. Miller, J M Sherman, J. HicksAbstract:In this paper, we present the results of multiple correlations between Reliability (infant mortality and other Reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with Reliability Defect density proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse Reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for Reliability failures.
J M Sherman - One of the best experts on this subject based on the ideXlab platform.
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microprocessor Reliability performance as a function of die location for a 0 25 spl mu five layer metal cmos logic process
International Reliability Physics Symposium, 1999Co-Authors: W.c. Riordan, R. Miller, J M Sherman, J. HicksAbstract:In this paper, we present the results of multiple correlations between Reliability (infant mortality and other Reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with Reliability Defect density proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse Reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for Reliability failures.
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Microprocessor Reliability performance as a function of die location for a 0.25 /spl mu/, five layer metal CMOS logic process
1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296), 1Co-Authors: W.c. Riordan, R. Miller, J M Sherman, J. HicksAbstract:In this paper, we present the results of multiple correlations between Reliability (infant mortality and other Reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with Reliability Defect density proportional to yield Defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse Reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for Reliability failures.
G. Digiacomo - One of the best experts on this subject based on the ideXlab platform.
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Reliability/Defect Severity
Microelectronics Manufacturing Diagnostics Handbook, 1993Co-Authors: G. DigiacomoAbstract:This chapter deals with the Reliability of micro-electronic components and semiconductors de-vices, how it is affected by Defects, and how to develop the proper Reliability testing and modeling leading to its improvement.