The Experts below are selected from a list of 181488 Experts worldwide ranked by ideXlab platform
Hu Guan - One of the best experts on this subject based on the ideXlab platform.
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Determination of volatile organic compounds in water with Retention Time locking in gas chromatograph
Environmental Monitoring in China, 2002Co-Authors: Hu GuanAbstract:The Retention Time data base was established with Retention Time Locking in gas chromatograph, which made it possible to qualitative analysis for fifty three kinds of volatile organic compounds in water The analysis was quick and simple
Abhinav Kranti - One of the best experts on this subject based on the ideXlab platform.
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improving Retention Time in tunnel field effect transistor based dynamic memory by back gate engineering
Journal of Applied Physics, 2016Co-Authors: Nupur Navlakha, Jyitsong Lin, Abhinav KrantiAbstract:In this work, we report on the impact of position, bias, and workfunction of back gate on Retention Time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the Retention Time. The Retention Time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The Retention Time attained is ∼2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the Retention Time of capacitorless dynamic memory.
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improving Retention Time in tunnel field effect transistor based dynamic memory by back gate engineering
Journal of Applied Physics, 2016Co-Authors: Nupur Navlakha, Abhinav KrantiAbstract:In this work, we report on the impact of position, bias, and workfunction of back gate on Retention Time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the Retention Time. The Retention Time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The Retention Time attained is ∼2 s at a temper...
Nupur Navlakha - One of the best experts on this subject based on the ideXlab platform.
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improving Retention Time in tunnel field effect transistor based dynamic memory by back gate engineering
Journal of Applied Physics, 2016Co-Authors: Nupur Navlakha, Jyitsong Lin, Abhinav KrantiAbstract:In this work, we report on the impact of position, bias, and workfunction of back gate on Retention Time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the Retention Time. The Retention Time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The Retention Time attained is ∼2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the Retention Time of capacitorless dynamic memory.
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improving Retention Time in tunnel field effect transistor based dynamic memory by back gate engineering
Journal of Applied Physics, 2016Co-Authors: Nupur Navlakha, Abhinav KrantiAbstract:In this work, we report on the impact of position, bias, and workfunction of back gate on Retention Time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the Retention Time. The Retention Time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The Retention Time attained is ∼2 s at a temper...
K.h. Yang - One of the best experts on this subject based on the ideXlab platform.
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Thermal degradation of DRAM Retention Time: Characterization and improving techniques
2004 IEEE International Reliability Physics Symposium. Proceedings, 2004Co-Authors: K.h. YangAbstract:Variation of DRAM Retention Time and reliability problem induced by thermal stress was investigated. Most of the DRAM cells revealed 2-state Retention Time with thermal stress. The effects of hydrogen annealing condition and fluorine implantation on the variation of Retention Time and reliability are discussed.
Byung-il Ryu - One of the best experts on this subject based on the ideXlab platform.
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Analysis of Thermal Variation of DRAM Retention Time
2006 IEEE International Reliability Physics Symposium Proceedings, 2006Co-Authors: Myoung-kwan Cho, Yung-soo Kim, D.s. Woo, S. Kim, Myoung-seob Shim, Young-kwan Park, Woung-moo Lee, Byung-il RyuAbstract:Variation of DRAM Retention Time induced by thermal stress was investigated. Thermal activation energies (Ea) of sub-threshold leakage, junction leakage and GIDL (Gate Induced Drain Leakage) current of a DRAM cell were measured using the test vehicles. The values were compared with Ea of 1/tREF for the DRAM cell of which the Retention Time had been varied after a thermal stress. Ea of 1/tREF for the thermally degraded DRAM cell was in the range of that for GIDL current, while Ea for the normal DRAM cells with high Retention Time was in the range of Ea for junction leakage. It is insisted that the thermal degradation of Retention Time is induced by increase in GIDL current. The contributions of gate oxide/substrate interface states to the GIDL current are discussed.