The Experts below are selected from a list of 225 Experts worldwide ranked by ideXlab platform
Konstantina Papagiannaki - One of the best experts on this subject based on the ideXlab platform.
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studying wireless Routing link metric dynamics
Internet Measurement Conference, 2007Co-Authors: Saumitra Mohan Das, Himabindu Pucha, Konstantina PapagiannakiAbstract:Multi-hop wireless mesh networks are increasingly being deployed for last-mile Internet access. Typically, network algorithms such as Routing, Channel assignment and topology control for such networks rely heavily on metrics that intend to capture link "quality" across the network. However, the underlying dynamics of the proposed link metrics themselves have not yet been studied in detail. In this paper, we study the dynamics of the most popular link metrics in real network deployments. Using two wireless mesh testbeds, we measure a number of link metrics across different hardware platforms and network environments. The collected measurements allow us to study the stability and sensitivity of the different metrics to various conditions. Our study provides several insights and future research directions on how network algorithms need to adapt to link dynamics as well as how popular and widely used link metrics can be improved.
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Internet Measurement Comference - Studying wireless Routing link metric dynamics
Proceedings of the 7th ACM SIGCOMM conference on Internet measurement - IMC '07, 2007Co-Authors: Saumitra Mohan Das, Himabindu Pucha, Konstantina PapagiannakiAbstract:Multi-hop wireless mesh networks are increasingly being deployed for last-mile Internet access. Typically, network algorithms such as Routing, Channel assignment and topology control for such networks rely heavily on metrics that intend to capture link "quality" across the network. However, the underlying dynamics of the proposed link metrics themselves have not yet been studied in detail. In this paper, we study the dynamics of the most popular link metrics in real network deployments. Using two wireless mesh testbeds, we measure a number of link metrics across different hardware platforms and network environments. The collected measurements allow us to study the stability and sensitivity of the different metrics to various conditions. Our study provides several insights and future research directions on how network algorithms need to adapt to link dynamics as well as how popular and widely used link metrics can be improved.
Zhi Huang - One of the best experts on this subject based on the ideXlab platform.
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a 3 8 mw gbps quad Channel 8 5 13 gbps serial link with a 5 tap dfe and a 4 tap transmit ffe in 28 nm cmos
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Namik Kocaman, Tamer Ali, Lakshmi Rao, Ullas Singh, Mohammed Abdullatif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi HuangAbstract:This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5–13 Gbps, implemented in 28 nm CMOS technology. The transmitter consists of 20:2 mux followed by a half-rate source-series terminated (SST) driver embedded with a 4 tap FFE and an analog equalizer. The receiver has an adaptive CTLE, 5 tap DFE, and fully digital CDR followed by 2:20 demux. At 13 Gbps, the transceiver can equalize 35 dB Nyquist loss at BER of 10-12. At 1.0 V supply, the transceiver consumes 49 mW/lane at 13 Gbps rate with full equalization capability. An LC VCO-based fractional PLL provides the clocking to quad TX/RX lanes using a low-power inductively tuned clock Routing Channel. The transceiver architecture not only enables the baud rate operation from 8.5 to 13 Gbps but also supports a wide range of oversampled subrates. This work represents the lowest reported power in its class to date, and the transceiver is suitable for many applications due to its comprehensive flexibility and power efficiency.
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a 3 8 mw gbps quad Channel 8 5 13 gbps serial link with a 5 tap dfe and a 4 tap transmit ffe in 28 nm cmos
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Namik Kocaman, Ullas Singh, Mohammed Abdullatif, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin MomtazAbstract:This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5–13 Gbps, implemented in 28 nm CMOS technology. The transmitter consists of 20:2 mux followed by a half-rate source-series terminated (SST) driver embedded with a 4 tap FFE and an analog equalizer. The receiver has an adaptive CTLE, 5 tap DFE, and fully digital CDR followed by 2:20 demux. At 13 Gbps, the transceiver can equalize 35 dB Nyquist loss at BER of 10-12. At 1.0 V supply, the transceiver consumes 49 mW/lane at 13 Gbps rate with full equalization capability. An LC VCO-based fractional PLL provides the clocking to quad TX/RX lanes using a low-power inductively tuned clock Routing Channel. The transceiver architecture not only enables the baud rate operation from 8.5 to 13 Gbps but also supports a wide range of oversampled subrates. This work represents the lowest reported power in its class to date, and the transceiver is suitable for many applications due to its comprehensive flexibility and power efficiency.
Allen Wu Yuhsheng C H Lee - One of the best experts on this subject based on the ideXlab platform.
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a performance and routability driven router for fpgas considering path delays
Design Automation Conference, 1995Co-Authors: Allen Wu Yuhsheng C H LeeAbstract:This paper presents a new performance and routability driven router for symmetrical array based Field Programmable Gate Arrays (FPGAs). The objectives of our proposed Routing algorithm are twofold: (1) improve the routability of the design (i.e., minimize the maximumrequired Routing Channel density) and (2) improve the overall performance of the design (i.e., minimize the overall path delay). Initially, nets are routed sequentially according to their criticalities and routabilities. The nets/paths violating the Routing-resource and timing constraints are then resolved iteratively by a rip-up-and-rerouter, which is guided by a simulated evolution based optimization technique. The proposed algorithm considers the path delays and routability throughout the entire Routing process. Experimental results show that our router can significantly improve routability and reduce delay over many existing Routing algorithms.
Saumitra Mohan Das - One of the best experts on this subject based on the ideXlab platform.
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studying wireless Routing link metric dynamics
Internet Measurement Conference, 2007Co-Authors: Saumitra Mohan Das, Himabindu Pucha, Konstantina PapagiannakiAbstract:Multi-hop wireless mesh networks are increasingly being deployed for last-mile Internet access. Typically, network algorithms such as Routing, Channel assignment and topology control for such networks rely heavily on metrics that intend to capture link "quality" across the network. However, the underlying dynamics of the proposed link metrics themselves have not yet been studied in detail. In this paper, we study the dynamics of the most popular link metrics in real network deployments. Using two wireless mesh testbeds, we measure a number of link metrics across different hardware platforms and network environments. The collected measurements allow us to study the stability and sensitivity of the different metrics to various conditions. Our study provides several insights and future research directions on how network algorithms need to adapt to link dynamics as well as how popular and widely used link metrics can be improved.
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Internet Measurement Comference - Studying wireless Routing link metric dynamics
Proceedings of the 7th ACM SIGCOMM conference on Internet measurement - IMC '07, 2007Co-Authors: Saumitra Mohan Das, Himabindu Pucha, Konstantina PapagiannakiAbstract:Multi-hop wireless mesh networks are increasingly being deployed for last-mile Internet access. Typically, network algorithms such as Routing, Channel assignment and topology control for such networks rely heavily on metrics that intend to capture link "quality" across the network. However, the underlying dynamics of the proposed link metrics themselves have not yet been studied in detail. In this paper, we study the dynamics of the most popular link metrics in real network deployments. Using two wireless mesh testbeds, we measure a number of link metrics across different hardware platforms and network environments. The collected measurements allow us to study the stability and sensitivity of the different metrics to various conditions. Our study provides several insights and future research directions on how network algorithms need to adapt to link dynamics as well as how popular and widely used link metrics can be improved.
Namik Kocaman - One of the best experts on this subject based on the ideXlab platform.
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a 3 8 mw gbps quad Channel 8 5 13 gbps serial link with a 5 tap dfe and a 4 tap transmit ffe in 28 nm cmos
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Namik Kocaman, Tamer Ali, Lakshmi Rao, Ullas Singh, Mohammed Abdullatif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi HuangAbstract:This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5–13 Gbps, implemented in 28 nm CMOS technology. The transmitter consists of 20:2 mux followed by a half-rate source-series terminated (SST) driver embedded with a 4 tap FFE and an analog equalizer. The receiver has an adaptive CTLE, 5 tap DFE, and fully digital CDR followed by 2:20 demux. At 13 Gbps, the transceiver can equalize 35 dB Nyquist loss at BER of 10-12. At 1.0 V supply, the transceiver consumes 49 mW/lane at 13 Gbps rate with full equalization capability. An LC VCO-based fractional PLL provides the clocking to quad TX/RX lanes using a low-power inductively tuned clock Routing Channel. The transceiver architecture not only enables the baud rate operation from 8.5 to 13 Gbps but also supports a wide range of oversampled subrates. This work represents the lowest reported power in its class to date, and the transceiver is suitable for many applications due to its comprehensive flexibility and power efficiency.
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a 3 8 mw gbps quad Channel 8 5 13 gbps serial link with a 5 tap dfe and a 4 tap transmit ffe in 28 nm cmos
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Namik Kocaman, Ullas Singh, Mohammed Abdullatif, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin MomtazAbstract:This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5–13 Gbps, implemented in 28 nm CMOS technology. The transmitter consists of 20:2 mux followed by a half-rate source-series terminated (SST) driver embedded with a 4 tap FFE and an analog equalizer. The receiver has an adaptive CTLE, 5 tap DFE, and fully digital CDR followed by 2:20 demux. At 13 Gbps, the transceiver can equalize 35 dB Nyquist loss at BER of 10-12. At 1.0 V supply, the transceiver consumes 49 mW/lane at 13 Gbps rate with full equalization capability. An LC VCO-based fractional PLL provides the clocking to quad TX/RX lanes using a low-power inductively tuned clock Routing Channel. The transceiver architecture not only enables the baud rate operation from 8.5 to 13 Gbps but also supports a wide range of oversampled subrates. This work represents the lowest reported power in its class to date, and the transceiver is suitable for many applications due to its comprehensive flexibility and power efficiency.
