The Experts below are selected from a list of 34149 Experts worldwide ranked by ideXlab platform
Guoqi Xie - One of the best experts on this subject based on the ideXlab platform.
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Price Performance-Driven Hardware Cost Optimization under Functional Safety Requirement in Large-Scale Heterogeneous Distributed Embedded Systems
IEEE Transactions on Industrial Electronics, 2021Co-Authors: Guoqi Xie, Hao PengAbstract:The problem of optimizing hardware cost un- der functional Safety Requirement is a desirable work for a Safety-critical embedded application. The state-of-the- art algorithms called enhanced explorative hardware cost optimization (EEHCO) and simplified EEHCO (SEEHCO) have been used to study this problem for a distributed embedded application by iteratively removing some pro- cessors from opened processors (i.e., open-to-close). How- ever, EEHCO has powerful cost optimization capability but inferior time efficiency, and vice versa for SEEHCO in large- scale heterogeneous distributed embedded systems. This study presents a price performance-driven hardware cost optimization (PPHCO) method, which is the combination of PPHCO1 and PPHCO2, to achieve powerful cost optimiza- tion capability and superior time efficiency simultaneously. PPHCO1 iteratively selects the processor with the maxi- mum price performance to open and overcomes the inferior time efficiency (i.e., close-to-open). PPHCO2 iteratively se- lects the processor with the minimum price performance to close and further optimizes the hardware cost on the basis of PPHCO1 without losing time efficiency (i.e., open-to- close). Through significantly reducing the iteration count, PPHCO overcomes the inferior time efficiency of the open- to-close method. Through adopting union fast functional Safety verification (UFFSV), PPHCO achieves powerful cost optimization capability. Experiments confirm that PPHCO not only achieves stronger cost optimization capability but also has better time efficiency than state-of-the-art EEHCO and SEEHCO algorithms.
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risk assessment and development cost optimization in software defined vehicles
IEEE Transactions on Intelligent Transportation Systems, 2020Co-Authors: Guoqi Xie, Gang ZengAbstract:Vehicle design has entered a new stage, namely, Software Defined Vehicles (SDV), where functional Safety is required to be guaranteed for risk control, and development cost needs to be optimized for profit maximization. This paper targets to optimize the development cost under the functional Safety Requirement for a Safety-aware SDV, based on the automotive Safety integrity level (ASIL) decomposition defined in ISO 26262. For this, a two-stage solution is proposed, which includes functional Safety risk assessment and development cost optimization. The first stage develops a new fast risk assessment (FRA) algorithm to assess the functional Safety risk, including the joint reliability risk and the real-time risk, of the SDV functionality. The second stage proposes a dual Requirement guarantee (DRG) algorithm to optimize the development cost considering reliability and real-time Requirements jointly. Our experiments demonstrate that the proposed two-stage solution guarantees the functional Safety Requirement while reducing the development cost by 20%-24%.
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Energy-Efficient Fault-Tolerant Scheduling of Reliable Parallel Applications on Heterogeneous Distributed Embedded Systems
IEEE Transactions on Sustainable Computing, 2018Co-Authors: Guoqi Xie, Yuekun Chen, Xiongren XiaoAbstract:Dynamic voltage and frequency scaling (DVFS) is a well-known energy consumption optimization technique in embedded systems and dynamically scaling down the voltage of a chip has been developed to achieve energy-efficient optimization. However, this operation may lead to a sharp rise in transient failures of processors and consequently weaken the reliability of systems. Reliability goal is an important functional Safety Requirement and must be satisfied for Safety-critical applications. In this study, we aim to implement energy-efficient fault-tolerant scheduling for a reliable parallel application on heterogeneous distributed embedded systems, where the parallel application is described by a directed acyclic graph (DAG). An energy-efficient scheduling with a reliability goal (ESRG) algorithm is presented to reduce the energy consumption while satisfying the reliability goal for the parallel application. Considering that the application's reliability goal is unreachable if its reliability goal exceeds a certain threshold via ESRG, we further propose an energy-efficient fault-tolerant scheduling with a reliability goal (EFSRG) algorithm to reduce the energy consumption while satisfying the reliability goal based on an active replication scheme. Experimental results confirm that the energy consumption reduced by the proposed EFSRG algorithm is higher than those reduced by other approaches under different scale conditions.
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Resource Consumption Cost Minimization of Reliable Parallel Applications on Heterogeneous Embedded Systems
IEEE Transactions on Industrial Informatics, 2017Co-Authors: Guoqi Xie, Yuekun Chen, Yan Liu, Yehua WeiAbstract:Heterogeneous processors are increasingly being used in embedded systems where parallel applications with precedence-constrained tasks widely exist. Reliability is an important functional Safety Requirement and reliability goal should be satisfied for Safety-critical parallel applications; meanwhile, resource is limited in embedded systems and it should be minimized. This study solves the problem of resource consumption cost minimization of a reliable parallel application on heterogeneous embedded systems without using fault tolerance. The problem is decomposed into two subproblems, namely, satisfying reliability goal and minimizing resource consumption cost. The first subproblem is solved by transferring the reliability goal of the application to that of each task, and the second subproblem is solved by heuristically assigning each task to the processor with the minimum resource consumption cost while satisfying its reliability goal. Experiments with real parallel applications verify that the proposed algorithm obtains minimum resource consumption costs compared with the state-of-the-art algorithms.
Yuekun Chen - One of the best experts on this subject based on the ideXlab platform.
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Energy-Efficient Fault-Tolerant Scheduling of Reliable Parallel Applications on Heterogeneous Distributed Embedded Systems
IEEE Transactions on Sustainable Computing, 2018Co-Authors: Guoqi Xie, Yuekun Chen, Xiongren XiaoAbstract:Dynamic voltage and frequency scaling (DVFS) is a well-known energy consumption optimization technique in embedded systems and dynamically scaling down the voltage of a chip has been developed to achieve energy-efficient optimization. However, this operation may lead to a sharp rise in transient failures of processors and consequently weaken the reliability of systems. Reliability goal is an important functional Safety Requirement and must be satisfied for Safety-critical applications. In this study, we aim to implement energy-efficient fault-tolerant scheduling for a reliable parallel application on heterogeneous distributed embedded systems, where the parallel application is described by a directed acyclic graph (DAG). An energy-efficient scheduling with a reliability goal (ESRG) algorithm is presented to reduce the energy consumption while satisfying the reliability goal for the parallel application. Considering that the application's reliability goal is unreachable if its reliability goal exceeds a certain threshold via ESRG, we further propose an energy-efficient fault-tolerant scheduling with a reliability goal (EFSRG) algorithm to reduce the energy consumption while satisfying the reliability goal based on an active replication scheme. Experimental results confirm that the energy consumption reduced by the proposed EFSRG algorithm is higher than those reduced by other approaches under different scale conditions.
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Hardware Cost Design Optimization for Functional Safety-Critical Parallel Applications on Heterogeneous Distributed Embedded Systems
IEEE Transactions on Industrial Informatics, 2018Co-Authors: Yuekun Chen, Renfa Li, Keqin LiAbstract:Industrial embedded systems are cost sensitive, and hardware cost of industrial production should be reduced for high profit. The functional Safety Requirement must be satisfied according to industrial functional Safety standards. This study proposes three hardware cost optimization algorithms for functional Safety-critical parallel applications on heterogeneous distributed embedded systems during the design phase. The explorative hardware cost optimization (EHCO), enhanced EHCO (EEHCO), and simplified EEHCO (SEEHCO) algorithms are proposed step by step. Experimental results reveal that EEHCO can obtain minimum hardware cost, whereas SEEHCO is efficient for large-scale parallel applications compared with the existing algorithms.
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Resource Consumption Cost Minimization of Reliable Parallel Applications on Heterogeneous Embedded Systems
IEEE Transactions on Industrial Informatics, 2017Co-Authors: Guoqi Xie, Yuekun Chen, Yan Liu, Yehua WeiAbstract:Heterogeneous processors are increasingly being used in embedded systems where parallel applications with precedence-constrained tasks widely exist. Reliability is an important functional Safety Requirement and reliability goal should be satisfied for Safety-critical parallel applications; meanwhile, resource is limited in embedded systems and it should be minimized. This study solves the problem of resource consumption cost minimization of a reliable parallel application on heterogeneous embedded systems without using fault tolerance. The problem is decomposed into two subproblems, namely, satisfying reliability goal and minimizing resource consumption cost. The first subproblem is solved by transferring the reliability goal of the application to that of each task, and the second subproblem is solved by heuristically assigning each task to the processor with the minimum resource consumption cost while satisfying its reliability goal. Experiments with real parallel applications verify that the proposed algorithm obtains minimum resource consumption costs compared with the state-of-the-art algorithms.
Martin Törngren - One of the best experts on this subject based on the ideXlab platform.
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modifi a model implemented fault injection tool
International Conference on Computer Safety Reliability and Security, 2010Co-Authors: Rickard Svenningsson, Henrik Eriksson, Jonny Vinter, Martin TörngrenAbstract:Fault injection is traditionally divided into simulation-based and physical techniques depending on whether faults are injected into hardware models, or into an actual physical system or prototype. Another classification is based on how fault injection mechanisms are implemented. Well known techniques are hardware-implemented fault injection (HIFI) and softwareimplemented fault injection (SWIFI). For Safety analyses during model-based development, fault injection mechanisms can be added directly into models of hardware, models of software or models of systems. This approach is denoted by the authors as model-implemented fault injection. This paper presents the MODIFI (MODel-Implemented Fault Injection) tool. The tool is currently targeting behaviour models in Simulink. Fault models used by MODIFI are defined using XML according to a specific schema file and the fault injection algorithm uses the concept of minimal cut sets (MCS) generation. First, a user defined set of single faults are injected to see if the system is tolerant against single faults. Single faults leading to a failure, i.e. a Safety Requirement violation, are stored in a MCS list together with the corresponding counterexample. These faults are also removed from the fault space used for subsequent experiments. When all single faults have been injected, the effects of multiple faults are investigated, i.e. two or more faults are introduced at the same time. The complete list of MCS is finally used to automatically generate test cases for efficient fault injection on the target system.
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Model-Implemented Fault Injection for Hardware Fault Simulation
2010 Workshop on Model-Driven Engineering Verification and Validation, 2010Co-Authors: Rickard Svenningsson, Henrik Eriksson, Jonny Vinter, Martin TörngrenAbstract:This paper presents how model-implemented fault injection can be utilized to simulate the effect of hardware-related faults in embedded systems. A fault injection environment has been developed to enable comparison of experiments at model level and hardware level using Simulink and an Infineon microcontroller, respectively. Experiments at model level, leading to Safety Requirement violations, are automatically repeated at hardware level to compare the fault effects. Artifacts in a Simulink model (e.g. block output ports) are automatically mapped to memory addresses obtained from a linker generated map file. Thus, the same variable can be manipulated by the fault injection environment at both model and hardware level. For the automotive application evaluated, experiments show that the effects of data errors at model level and hardware level are similar excluding the experiments leading to exceptions.
Keqin Li - One of the best experts on this subject based on the ideXlab platform.
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Hardware Cost Design Optimization for Functional Safety-Critical Parallel Applications on Heterogeneous Distributed Embedded Systems
IEEE Transactions on Industrial Informatics, 2018Co-Authors: Yuekun Chen, Renfa Li, Keqin LiAbstract:Industrial embedded systems are cost sensitive, and hardware cost of industrial production should be reduced for high profit. The functional Safety Requirement must be satisfied according to industrial functional Safety standards. This study proposes three hardware cost optimization algorithms for functional Safety-critical parallel applications on heterogeneous distributed embedded systems during the design phase. The explorative hardware cost optimization (EHCO), enhanced EHCO (EEHCO), and simplified EEHCO (SEEHCO) algorithms are proposed step by step. Experimental results reveal that EEHCO can obtain minimum hardware cost, whereas SEEHCO is efficient for large-scale parallel applications compared with the existing algorithms.
Xiongren Xiao - One of the best experts on this subject based on the ideXlab platform.
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Energy-Efficient Fault-Tolerant Scheduling of Reliable Parallel Applications on Heterogeneous Distributed Embedded Systems
IEEE Transactions on Sustainable Computing, 2018Co-Authors: Guoqi Xie, Yuekun Chen, Xiongren XiaoAbstract:Dynamic voltage and frequency scaling (DVFS) is a well-known energy consumption optimization technique in embedded systems and dynamically scaling down the voltage of a chip has been developed to achieve energy-efficient optimization. However, this operation may lead to a sharp rise in transient failures of processors and consequently weaken the reliability of systems. Reliability goal is an important functional Safety Requirement and must be satisfied for Safety-critical applications. In this study, we aim to implement energy-efficient fault-tolerant scheduling for a reliable parallel application on heterogeneous distributed embedded systems, where the parallel application is described by a directed acyclic graph (DAG). An energy-efficient scheduling with a reliability goal (ESRG) algorithm is presented to reduce the energy consumption while satisfying the reliability goal for the parallel application. Considering that the application's reliability goal is unreachable if its reliability goal exceeds a certain threshold via ESRG, we further propose an energy-efficient fault-tolerant scheduling with a reliability goal (EFSRG) algorithm to reduce the energy consumption while satisfying the reliability goal based on an active replication scheme. Experimental results confirm that the energy consumption reduced by the proposed EFSRG algorithm is higher than those reduced by other approaches under different scale conditions.
