Sampling Circuit

14,000,000 Leading Edge Experts on the ideXlab platform

Scan Science and Technology

Contact Leading Edge Experts & Companies

Scan Science and Technology

Contact Leading Edge Experts & Companies

The Experts below are selected from a list of 13989 Experts worldwide ranked by ideXlab platform

Andreas Demosthenous - One of the best experts on this subject based on the ideXlab platform.

  • constant resistance cmos input Sampling switch for gsm wcdma high dynamic range delta sigma modulators
    IEEE Transactions on Circuits and Systems I-regular Papers, 2008
    Co-Authors: Olujide A. Adeniran, Andreas Demosthenous
    Abstract:

    The nonlinearity of the input Sampling switch in a switched-capacitor delta-sigma (DeltaSigma) analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS switch is proposed in this paper. A linearized CMOS switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling Circuit, compared to using a standard CMOS switch or a bootstrapped nMOS switch. The dynamic range improvement achieved as a result of the proposed technique is validated with the design of two high dynamic range fourth-order switched-capacitor DeltaSigma modulators for GSM and WCDMA radio standards in a 0.35-mum BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm2 .

  • constant resistance cmos input Sampling switch for gsm wcdma high dynamic range modulators
    2008
    Co-Authors: Olujide A. Adeniran, Andreas Demosthenous
    Abstract:

    The nonlinearity of the input Sampling switch in a switched-capacitor delta-sigma analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS switch is proposed in this paper. A linearized CMOS switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling Circuit, compared to using a standard CMOS switch or a bootstrapped nMOS switch. The dynamic range improvement achieved as a result of the pro- posed technique is validated with the design of two high dynamic range fourth-order switched-capacitor modulators for GSM and WCDMA radio standards in a 0.35- m BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm . Index Terms—Analog-to-digital conversion (ADC), bootstrap Circuit, CMOS switch linearization, delta-sigma modulation, GSM, nonlinearity, radio receivers, switched-capacitor Circuits, WCDMA.

Olujide A. Adeniran - One of the best experts on this subject based on the ideXlab platform.

  • constant resistance cmos input Sampling switch for gsm wcdma high dynamic range delta sigma modulators
    IEEE Transactions on Circuits and Systems I-regular Papers, 2008
    Co-Authors: Olujide A. Adeniran, Andreas Demosthenous
    Abstract:

    The nonlinearity of the input Sampling switch in a switched-capacitor delta-sigma (DeltaSigma) analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS switch is proposed in this paper. A linearized CMOS switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling Circuit, compared to using a standard CMOS switch or a bootstrapped nMOS switch. The dynamic range improvement achieved as a result of the proposed technique is validated with the design of two high dynamic range fourth-order switched-capacitor DeltaSigma modulators for GSM and WCDMA radio standards in a 0.35-mum BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm2 .

  • constant resistance cmos input Sampling switch for gsm wcdma high dynamic range modulators
    2008
    Co-Authors: Olujide A. Adeniran, Andreas Demosthenous
    Abstract:

    The nonlinearity of the input Sampling switch in a switched-capacitor delta-sigma analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS switch is proposed in this paper. A linearized CMOS switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a Sampling Circuit, compared to using a standard CMOS switch or a bootstrapped nMOS switch. The dynamic range improvement achieved as a result of the pro- posed technique is validated with the design of two high dynamic range fourth-order switched-capacitor modulators for GSM and WCDMA radio standards in a 0.35- m BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm . Index Terms—Analog-to-digital conversion (ADC), bootstrap Circuit, CMOS switch linearization, delta-sigma modulation, GSM, nonlinearity, radio receivers, switched-capacitor Circuits, WCDMA.

Wu Jingyue - One of the best experts on this subject based on the ideXlab platform.

  • improve single phase vienna rectifier mid point voltage unbalance s rectifier Circuit
    2016
    Co-Authors: Kang Longyun, Ping Teng, Li Zhen, Wu Jingyue
    Abstract:

    The utility model discloses an improve single -phase vienna rectifier mid point voltage unbalance's rectifier Circuit, including a LC controlable electric current, the 2nd LC controlable electric current, Sampling Circuit, auxiliary power supply module, single -chip computer control module and drive module, Sampling Circuit gathers the upper portion mid point current potential un1 and the lower part mid point current potential un2 of the rectifier output of single -phase vienna, single -chip computer control module calculates back outlet driving signal to drive module, the drive signal of drive module output transmits respectively to a LC controlable electric current, the 2nd LC controlable electric current, change a LC controlable electric current, the 2nd LC controlable electric current move the phase angle, then make un1 through the negative feedback, un2 automatically regulated, compensate the unbalanced mid point voltage of single -phase vienna rectifier, until the balance. The utility model discloses a rectifier Circuit adjusts output capacitance access value in real time, reaches the effect of automatic compensation mid point current potential, has effectively solved vienna rectifier Circuit's the unbalanced problem of mid point current potential.

  • improve vienna rectifier mid point voltage unbalance s rectifier Circuit
    2016
    Co-Authors: Kang Longyun, Wu Jingyue, Li Zhen, Wang Shubiao
    Abstract:

    The utility model discloses an improve vienna rectifier mid point voltage unbalance's rectifier Circuit, including a LC controlable electric current, the 2nd LC controlable electric current, Sampling Circuit, auxiliary power supply module, single -chip?computer?control?module and drive module, Sampling Circuit gathers the upper portion mid point current potential un1 of vienna rectifier output, the lower part mid point current potential un2 of vienna rectifier output, single -chip?computer?control?module is outlet driving signal to drive module in view of the above, the drive signal of drive module output transmits respectively to a LC controlable electric current, the 2nd LC controlable electric current, change a LC controlable electric current, the 2nd LC controlable electric current move the phase angle, make un1 through the negative feedback, un2 automatically regulated, the unbalanced mid point voltage of compensation vienna rectifier, until the balance. The utility model discloses a rectifier Circuit, the real time control LC controlable electric current move the phase angle, compensate unbalanced mid point voltage, realize the function of the automatically regulated mid point balance of voltage.

Kang Longyun - One of the best experts on this subject based on the ideXlab platform.

  • improve single phase vienna rectifier mid point voltage unbalance s rectifier Circuit
    2016
    Co-Authors: Kang Longyun, Ping Teng, Li Zhen, Wu Jingyue
    Abstract:

    The utility model discloses an improve single -phase vienna rectifier mid point voltage unbalance's rectifier Circuit, including a LC controlable electric current, the 2nd LC controlable electric current, Sampling Circuit, auxiliary power supply module, single -chip computer control module and drive module, Sampling Circuit gathers the upper portion mid point current potential un1 and the lower part mid point current potential un2 of the rectifier output of single -phase vienna, single -chip computer control module calculates back outlet driving signal to drive module, the drive signal of drive module output transmits respectively to a LC controlable electric current, the 2nd LC controlable electric current, change a LC controlable electric current, the 2nd LC controlable electric current move the phase angle, then make un1 through the negative feedback, un2 automatically regulated, compensate the unbalanced mid point voltage of single -phase vienna rectifier, until the balance. The utility model discloses a rectifier Circuit adjusts output capacitance access value in real time, reaches the effect of automatic compensation mid point current potential, has effectively solved vienna rectifier Circuit's the unbalanced problem of mid point current potential.

  • improve vienna rectifier mid point voltage unbalance s rectifier Circuit
    2016
    Co-Authors: Kang Longyun, Wu Jingyue, Li Zhen, Wang Shubiao
    Abstract:

    The utility model discloses an improve vienna rectifier mid point voltage unbalance's rectifier Circuit, including a LC controlable electric current, the 2nd LC controlable electric current, Sampling Circuit, auxiliary power supply module, single -chip?computer?control?module and drive module, Sampling Circuit gathers the upper portion mid point current potential un1 of vienna rectifier output, the lower part mid point current potential un2 of vienna rectifier output, single -chip?computer?control?module is outlet driving signal to drive module in view of the above, the drive signal of drive module output transmits respectively to a LC controlable electric current, the 2nd LC controlable electric current, change a LC controlable electric current, the 2nd LC controlable electric current move the phase angle, make un1 through the negative feedback, un2 automatically regulated, the unbalanced mid point voltage of compensation vienna rectifier, until the balance. The utility model discloses a rectifier Circuit, the real time control LC controlable electric current move the phase angle, compensate unbalanced mid point voltage, realize the function of the automatically regulated mid point balance of voltage.

Wang Shubiao - One of the best experts on this subject based on the ideXlab platform.

  • improve vienna rectifier mid point voltage unbalance s rectifier Circuit
    2016
    Co-Authors: Kang Longyun, Wu Jingyue, Li Zhen, Wang Shubiao
    Abstract:

    The utility model discloses an improve vienna rectifier mid point voltage unbalance's rectifier Circuit, including a LC controlable electric current, the 2nd LC controlable electric current, Sampling Circuit, auxiliary power supply module, single -chip?computer?control?module and drive module, Sampling Circuit gathers the upper portion mid point current potential un1 of vienna rectifier output, the lower part mid point current potential un2 of vienna rectifier output, single -chip?computer?control?module is outlet driving signal to drive module in view of the above, the drive signal of drive module output transmits respectively to a LC controlable electric current, the 2nd LC controlable electric current, change a LC controlable electric current, the 2nd LC controlable electric current move the phase angle, make un1 through the negative feedback, un2 automatically regulated, the unbalanced mid point voltage of compensation vienna rectifier, until the balance. The utility model discloses a rectifier Circuit, the real time control LC controlable electric current move the phase angle, compensate unbalanced mid point voltage, realize the function of the automatically regulated mid point balance of voltage.