The Experts below are selected from a list of 78 Experts worldwide ranked by ideXlab platform
E J Mccluskey - One of the best experts on this subject based on the ideXlab platform.
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Error detection by duplicated instructions in super-Scalar Processors
IEEE Transactions on Reliability, 2002Co-Authors: N. Oh, P.p. Shirvani, E J MccluskeyAbstract:This paper proposes a pure software technique "error detection by duplicated instructions" (EDDI), for detecting errors during usual system operation. Compared to other error-detection techniques that use hardware redundancy, EDDI does not require any hardware modifications to add error detection capability to the original system. EDDI duplicates instructions during compilation and uses different registers and variables for the new instructions. Especially for the fault in the code segment of memory, formulas are derived to estimate the error-detection coverage of EDDI using probabilistic methods. These formulas use statistics of the program, which are collected during compilation. EDDI was applied to eight benchmark programs and the error-detection coverage was estimated. Then, the estimates were verified by simulation, in which a fault injector forced a bit-flip in the code segment of executable machine codes. The simulation results validated the estimated fault coverage and show that approximately 1.5% of injected faults produced incorrect results in eight benchmark programs with EDDI, while on average, 20% of injected faults produced undetected incorrect results in the programs without EDDI. Based on the theoretical estimates and actual fault-injection experiments, EDDI can provide over 98% fault-coverage without any extra hardware for error detection. This pure software technique is especially useful when designers cannot change the hardware, but they need dependability in the computer system. To reduce the performance overhead, EDDI schedules the instructions that are added for detecting errors such that "instruction-level parallelism" (ILP) is maximized. Performance overhead can be reduced by increasing ILP within a single super-Scalar Processor. The execution time overhead in a 4-way super-Scalar Processor is less than the execution time overhead in the Processors that can issue two instructions in one cycle.
Tag Gon Kim - One of the best experts on this subject based on the ideXlab platform.
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performance simulation modeling for fast evaluation of pipelined Scalar Processor by evaluation reuse
Design Automation Conference, 2005Co-Authors: Hoyoung Kim, Tag Gon KimAbstract:This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined Processor using evaluation reuse technique. Since exploration of an optimal Processor is a time-consuming task due to large design space, fast evaluation methodology for an architecture is crucial. We introduce the performance simulation model which can evaluate the performance without considering the functional correctness. This model has an FSM-like form and can afford to take all hazard types of pipelined architectures into consideration. The proposed approach is based on the property that an application program, especially multimedia application, has many iterative loops in general. This property invokes many iterative operations in the simulation. Evaluation reuse scheme can alleviate redundantly iterative operations of conventional simulators in the loop. A performance simulator for the pipeline architecture has been developed through which greater speedup has been made compared with other approaches in the evaluation of cycle counts.
N. Oh - One of the best experts on this subject based on the ideXlab platform.
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Error detection by duplicated instructions in super-Scalar Processors
IEEE Transactions on Reliability, 2002Co-Authors: N. Oh, P.p. Shirvani, E J MccluskeyAbstract:This paper proposes a pure software technique "error detection by duplicated instructions" (EDDI), for detecting errors during usual system operation. Compared to other error-detection techniques that use hardware redundancy, EDDI does not require any hardware modifications to add error detection capability to the original system. EDDI duplicates instructions during compilation and uses different registers and variables for the new instructions. Especially for the fault in the code segment of memory, formulas are derived to estimate the error-detection coverage of EDDI using probabilistic methods. These formulas use statistics of the program, which are collected during compilation. EDDI was applied to eight benchmark programs and the error-detection coverage was estimated. Then, the estimates were verified by simulation, in which a fault injector forced a bit-flip in the code segment of executable machine codes. The simulation results validated the estimated fault coverage and show that approximately 1.5% of injected faults produced incorrect results in eight benchmark programs with EDDI, while on average, 20% of injected faults produced undetected incorrect results in the programs without EDDI. Based on the theoretical estimates and actual fault-injection experiments, EDDI can provide over 98% fault-coverage without any extra hardware for error detection. This pure software technique is especially useful when designers cannot change the hardware, but they need dependability in the computer system. To reduce the performance overhead, EDDI schedules the instructions that are added for detecting errors such that "instruction-level parallelism" (ILP) is maximized. Performance overhead can be reduced by increasing ILP within a single super-Scalar Processor. The execution time overhead in a 4-way super-Scalar Processor is less than the execution time overhead in the Processors that can issue two instructions in one cycle.
P.p. Shirvani - One of the best experts on this subject based on the ideXlab platform.
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Error detection by duplicated instructions in super-Scalar Processors
IEEE Transactions on Reliability, 2002Co-Authors: N. Oh, P.p. Shirvani, E J MccluskeyAbstract:This paper proposes a pure software technique "error detection by duplicated instructions" (EDDI), for detecting errors during usual system operation. Compared to other error-detection techniques that use hardware redundancy, EDDI does not require any hardware modifications to add error detection capability to the original system. EDDI duplicates instructions during compilation and uses different registers and variables for the new instructions. Especially for the fault in the code segment of memory, formulas are derived to estimate the error-detection coverage of EDDI using probabilistic methods. These formulas use statistics of the program, which are collected during compilation. EDDI was applied to eight benchmark programs and the error-detection coverage was estimated. Then, the estimates were verified by simulation, in which a fault injector forced a bit-flip in the code segment of executable machine codes. The simulation results validated the estimated fault coverage and show that approximately 1.5% of injected faults produced incorrect results in eight benchmark programs with EDDI, while on average, 20% of injected faults produced undetected incorrect results in the programs without EDDI. Based on the theoretical estimates and actual fault-injection experiments, EDDI can provide over 98% fault-coverage without any extra hardware for error detection. This pure software technique is especially useful when designers cannot change the hardware, but they need dependability in the computer system. To reduce the performance overhead, EDDI schedules the instructions that are added for detecting errors such that "instruction-level parallelism" (ILP) is maximized. Performance overhead can be reduced by increasing ILP within a single super-Scalar Processor. The execution time overhead in a 4-way super-Scalar Processor is less than the execution time overhead in the Processors that can issue two instructions in one cycle.
Hoyoung Kim - One of the best experts on this subject based on the ideXlab platform.
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performance simulation modeling for fast evaluation of pipelined Scalar Processor by evaluation reuse
Design Automation Conference, 2005Co-Authors: Hoyoung Kim, Tag Gon KimAbstract:This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined Processor using evaluation reuse technique. Since exploration of an optimal Processor is a time-consuming task due to large design space, fast evaluation methodology for an architecture is crucial. We introduce the performance simulation model which can evaluate the performance without considering the functional correctness. This model has an FSM-like form and can afford to take all hazard types of pipelined architectures into consideration. The proposed approach is based on the property that an application program, especially multimedia application, has many iterative loops in general. This property invokes many iterative operations in the simulation. Evaluation reuse scheme can alleviate redundantly iterative operations of conventional simulators in the loop. A performance simulator for the pipeline architecture has been developed through which greater speedup has been made compared with other approaches in the evaluation of cycle counts.
