The Experts below are selected from a list of 51066 Experts worldwide ranked by ideXlab platform
Todd C Mowry - One of the best experts on this subject based on the ideXlab platform.
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Compiler Optimization of MemoryResident Value Communication Between Speculative Threads
2018Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in thread-level speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values. In TLS, data dependences through memory-resident Values are tracked by the underlying hardware and preserved by re-executing any speculative thread that violates a dependence; however, re-execution incurs a large performance penalty and should be used only to resolve data dependences that are infrequent. In contrast, Value communication for frequently-occurring data dependences must be very efficient. We propose using the compiler to first identify frequently-occurring memory-resident data dependences, then insert synchronization for communicating Values to preserve these dependences. We find that by synchronizing frequently-occurring data dependences we can significantly improve the efficiency of parallel execution. A comparison between compiler-inserted and hardware-inserted memory synchronization reveals that the two techniques are complementary, with each technique benefitting different benchmarks
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compiler optimization of memory resident Value communication between speculative threads
Symposium on Code Generation and Optimization, 2004Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in thread-level speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values. In TLS, data dependences through memory-resident Values are tracked by the underlying hardware and preserved by re-executing any speculative thread that violates a dependence; however, re-execution incurs a large performance penalty and should be used only to resolve data dependences that are infrequent. In contrast, Value communication for frequently-occurring data dependences must be very efficient. We propose using the compiler to first identify frequently-occurring memory-resident data dependences, then insert synchronization for communicating Values to preserve these dependences. We find that by synchronizing frequently-occurring data dependences we can significantly improve the efficiency of parallel execution. A comparison between compiler-inserted and hardware-inserted memory synchronization reveals that the two techniques are complementary, with each technique benefitting different benchmarks.
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Compiler Optimization of Memory-Resident Value Communication between Speculative Threads
2004Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in Thread-Level Speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values
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compiler optimization of Scalar Value communication between speculative threads
Architectural Support for Programming Languages and Operating Systems, 2002Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this paper, we focus on one important limitation of program performance under TLS, which is stalls due to forwarding Scalar Values between threads that would otherwise cause frequent data dependences. We present and evaluate dataflow algorithms for three increasingly-aggressive instruction scheduling techniques that reduce the critical forwarding path introduced by the synchronization associated with this data forwarding. In addition, we contrast our compiler techniques with related hardware-only approaches. With our most aggressive compiler and hardware techniques, we improve performance under TLS by 6.2-28.5% for 6 of 14 applications, and by at least 2.7% for half of the other applications.
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ASPLOS - Compiler optimization of Scalar Value communication between speculative threads
Tenth international conference on architectural support for programming languages and operating systems on Proceedings of the 10th international confe, 2002Co-Authors: Antonia Zhai, Christopher B Colohan, J. Gregory Steffan, Todd C MowryAbstract:While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this paper, we focus on one important limitation of program performance under TLS, which is stalls due to forwarding Scalar Values between threads that would otherwise cause frequent data dependences. We present and evaluate dataflow algorithms for three increasingly-aggressive instruction scheduling techniques that reduce the critical forwarding path introduced by the synchronization associated with this data forwarding. In addition, we contrast our compiler techniques with related hardware-only approaches. With our most aggressive compiler and hardware techniques, we improve performance under TLS by 6.2-28.5% for 6 of 14 applications, and by at least 2.7% for half of the other applications.
Antonia Zhai - One of the best experts on this subject based on the ideXlab platform.
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Compiler Optimization of MemoryResident Value Communication Between Speculative Threads
2018Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in thread-level speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values. In TLS, data dependences through memory-resident Values are tracked by the underlying hardware and preserved by re-executing any speculative thread that violates a dependence; however, re-execution incurs a large performance penalty and should be used only to resolve data dependences that are infrequent. In contrast, Value communication for frequently-occurring data dependences must be very efficient. We propose using the compiler to first identify frequently-occurring memory-resident data dependences, then insert synchronization for communicating Values to preserve these dependences. We find that by synchronizing frequently-occurring data dependences we can significantly improve the efficiency of parallel execution. A comparison between compiler-inserted and hardware-inserted memory synchronization reveals that the two techniques are complementary, with each technique benefitting different benchmarks
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compiler optimization of memory resident Value communication between speculative threads
Symposium on Code Generation and Optimization, 2004Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in thread-level speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values. In TLS, data dependences through memory-resident Values are tracked by the underlying hardware and preserved by re-executing any speculative thread that violates a dependence; however, re-execution incurs a large performance penalty and should be used only to resolve data dependences that are infrequent. In contrast, Value communication for frequently-occurring data dependences must be very efficient. We propose using the compiler to first identify frequently-occurring memory-resident data dependences, then insert synchronization for communicating Values to preserve these dependences. We find that by synchronizing frequently-occurring data dependences we can significantly improve the efficiency of parallel execution. A comparison between compiler-inserted and hardware-inserted memory synchronization reveals that the two techniques are complementary, with each technique benefitting different benchmarks.
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Compiler Optimization of Memory-Resident Value Communication between Speculative Threads
2004Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in Thread-Level Speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values
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compiler optimization of Scalar Value communication between speculative threads
Architectural Support for Programming Languages and Operating Systems, 2002Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this paper, we focus on one important limitation of program performance under TLS, which is stalls due to forwarding Scalar Values between threads that would otherwise cause frequent data dependences. We present and evaluate dataflow algorithms for three increasingly-aggressive instruction scheduling techniques that reduce the critical forwarding path introduced by the synchronization associated with this data forwarding. In addition, we contrast our compiler techniques with related hardware-only approaches. With our most aggressive compiler and hardware techniques, we improve performance under TLS by 6.2-28.5% for 6 of 14 applications, and by at least 2.7% for half of the other applications.
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ASPLOS - Compiler optimization of Scalar Value communication between speculative threads
Tenth international conference on architectural support for programming languages and operating systems on Proceedings of the 10th international confe, 2002Co-Authors: Antonia Zhai, Christopher B Colohan, J. Gregory Steffan, Todd C MowryAbstract:While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this paper, we focus on one important limitation of program performance under TLS, which is stalls due to forwarding Scalar Values between threads that would otherwise cause frequent data dependences. We present and evaluate dataflow algorithms for three increasingly-aggressive instruction scheduling techniques that reduce the critical forwarding path introduced by the synchronization associated with this data forwarding. In addition, we contrast our compiler techniques with related hardware-only approaches. With our most aggressive compiler and hardware techniques, we improve performance under TLS by 6.2-28.5% for 6 of 14 applications, and by at least 2.7% for half of the other applications.
Stavros Tavoularis - One of the best experts on this subject based on the ideXlab platform.
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Scalar probability density function and fine structure in uniformly sheared turbulence
Journal of Fluid Mechanics, 2002Co-Authors: M. Ferchichi, Stavros TavoularisAbstract:This study is an experimental investigation of the probability density function (p.d.f.) and the fine structure of temperature fluctuations in uniformly sheared turbulence with a passively introduced uniform mean temperature gradient. The shear parameter was relatively large, resulting in vigorous turbulence production and a total mean strain up to 23. The turbulence Reynolds number was up to 253. The Scalar fluctuations grew in a self-similar fashion and at the same exponential rate as the turbulence stresses, in conformity with predictions based on an analytical solution of the Scalar variance equation. Analytical considerations as well as measurements demonstrate that the Scalar p.d.f. is essentially Gaussian and that the Scalar–velocity joint p.d.f. is essentially jointly Gaussian, with the conditional expectations of the velocity fluctuations linearly dependent on the Scalar Value. Joint statistics of the Scalar and its dissipation rate indicate a statistical independence of the two parameters. The fine structure of the Scalar was invoked from statistics of derivatives and differences of the Scalar, in both the streamwise and transverse directions. Probability density functions of Scalar derivatives and differences in the dissipative and the inertial ranges were strongly non-Gaussian and skewed, displaying flared, asymmetric tails. All measurements point to a highly intermittent Scalar fine structure, even more intermittent than the fine structure of the turbulent velocity.
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PDF of Temperature Fluctuations in Uniformly Sheared Turbulence
IUTAM Symposium on Turbulent Mixing and Combustion, 2002Co-Authors: M. Ferchichi, Stavros TavoularisAbstract:Statistics of temperature fluctuations were measured in uniformly sheared turbulence with a uniform mean temperature gradient. The Scalar pdf was Gaussian and the Scalar-velocity joint pdf was jointly Gaussian, with the conditional expectations of the velocity fluctuations linearly dependent on the Scalar Value. The Scalar dissipation rate was statistically independent from the Scalar Value. A Gaussian Scalar pdf was also predicted analytically.
Christopher B Colohan - One of the best experts on this subject based on the ideXlab platform.
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Compiler Optimization of MemoryResident Value Communication Between Speculative Threads
2018Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in thread-level speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values. In TLS, data dependences through memory-resident Values are tracked by the underlying hardware and preserved by re-executing any speculative thread that violates a dependence; however, re-execution incurs a large performance penalty and should be used only to resolve data dependences that are infrequent. In contrast, Value communication for frequently-occurring data dependences must be very efficient. We propose using the compiler to first identify frequently-occurring memory-resident data dependences, then insert synchronization for communicating Values to preserve these dependences. We find that by synchronizing frequently-occurring data dependences we can significantly improve the efficiency of parallel execution. A comparison between compiler-inserted and hardware-inserted memory synchronization reveals that the two techniques are complementary, with each technique benefitting different benchmarks
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compiler optimization of memory resident Value communication between speculative threads
Symposium on Code Generation and Optimization, 2004Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in thread-level speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values. In TLS, data dependences through memory-resident Values are tracked by the underlying hardware and preserved by re-executing any speculative thread that violates a dependence; however, re-execution incurs a large performance penalty and should be used only to resolve data dependences that are infrequent. In contrast, Value communication for frequently-occurring data dependences must be very efficient. We propose using the compiler to first identify frequently-occurring memory-resident data dependences, then insert synchronization for communicating Values to preserve these dependences. We find that by synchronizing frequently-occurring data dependences we can significantly improve the efficiency of parallel execution. A comparison between compiler-inserted and hardware-inserted memory synchronization reveals that the two techniques are complementary, with each technique benefitting different benchmarks.
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Compiler Optimization of Memory-Resident Value Communication between Speculative Threads
2004Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in Thread-Level Speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values
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compiler optimization of Scalar Value communication between speculative threads
Architectural Support for Programming Languages and Operating Systems, 2002Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this paper, we focus on one important limitation of program performance under TLS, which is stalls due to forwarding Scalar Values between threads that would otherwise cause frequent data dependences. We present and evaluate dataflow algorithms for three increasingly-aggressive instruction scheduling techniques that reduce the critical forwarding path introduced by the synchronization associated with this data forwarding. In addition, we contrast our compiler techniques with related hardware-only approaches. With our most aggressive compiler and hardware techniques, we improve performance under TLS by 6.2-28.5% for 6 of 14 applications, and by at least 2.7% for half of the other applications.
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ASPLOS - Compiler optimization of Scalar Value communication between speculative threads
Tenth international conference on architectural support for programming languages and operating systems on Proceedings of the 10th international confe, 2002Co-Authors: Antonia Zhai, Christopher B Colohan, J. Gregory Steffan, Todd C MowryAbstract:While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this paper, we focus on one important limitation of program performance under TLS, which is stalls due to forwarding Scalar Values between threads that would otherwise cause frequent data dependences. We present and evaluate dataflow algorithms for three increasingly-aggressive instruction scheduling techniques that reduce the critical forwarding path introduced by the synchronization associated with this data forwarding. In addition, we contrast our compiler techniques with related hardware-only approaches. With our most aggressive compiler and hardware techniques, we improve performance under TLS by 6.2-28.5% for 6 of 14 applications, and by at least 2.7% for half of the other applications.
Gregory J Steffan - One of the best experts on this subject based on the ideXlab platform.
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Compiler Optimization of MemoryResident Value Communication Between Speculative Threads
2018Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in thread-level speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values. In TLS, data dependences through memory-resident Values are tracked by the underlying hardware and preserved by re-executing any speculative thread that violates a dependence; however, re-execution incurs a large performance penalty and should be used only to resolve data dependences that are infrequent. In contrast, Value communication for frequently-occurring data dependences must be very efficient. We propose using the compiler to first identify frequently-occurring memory-resident data dependences, then insert synchronization for communicating Values to preserve these dependences. We find that by synchronizing frequently-occurring data dependences we can significantly improve the efficiency of parallel execution. A comparison between compiler-inserted and hardware-inserted memory synchronization reveals that the two techniques are complementary, with each technique benefitting different benchmarks
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compiler optimization of memory resident Value communication between speculative threads
Symposium on Code Generation and Optimization, 2004Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in thread-level speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values. In TLS, data dependences through memory-resident Values are tracked by the underlying hardware and preserved by re-executing any speculative thread that violates a dependence; however, re-execution incurs a large performance penalty and should be used only to resolve data dependences that are infrequent. In contrast, Value communication for frequently-occurring data dependences must be very efficient. We propose using the compiler to first identify frequently-occurring memory-resident data dependences, then insert synchronization for communicating Values to preserve these dependences. We find that by synchronizing frequently-occurring data dependences we can significantly improve the efficiency of parallel execution. A comparison between compiler-inserted and hardware-inserted memory synchronization reveals that the two techniques are complementary, with each technique benefitting different benchmarks.
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Compiler Optimization of Memory-Resident Value Communication between Speculative Threads
2004Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:Efficient inter-thread Value communication is essential for improving performance in Thread-Level Speculation (TLS). Although several mechanisms for improving Value communication using hardware support have been proposed, there is relatively little work on exploiting the potential of compiler optimization. Building on recent research on compiler optimization of Scalar Value communication between speculative threads, we propose compiler techniques for the optimization of memory-resident Values
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compiler optimization of Scalar Value communication between speculative threads
Architectural Support for Programming Languages and Operating Systems, 2002Co-Authors: Antonia Zhai, Christopher B Colohan, Gregory J Steffan, Todd C MowryAbstract:While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this paper, we focus on one important limitation of program performance under TLS, which is stalls due to forwarding Scalar Values between threads that would otherwise cause frequent data dependences. We present and evaluate dataflow algorithms for three increasingly-aggressive instruction scheduling techniques that reduce the critical forwarding path introduced by the synchronization associated with this data forwarding. In addition, we contrast our compiler techniques with related hardware-only approaches. With our most aggressive compiler and hardware techniques, we improve performance under TLS by 6.2-28.5% for 6 of 14 applications, and by at least 2.7% for half of the other applications.
