The Experts below are selected from a list of 252 Experts worldwide ranked by ideXlab platform
David I. August - One of the best experts on this subject based on the ideXlab platform.
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CASES - From Sequential Programming to flexible parallel execution
Proceedings of the 2012 international conference on Compilers architectures and synthesis for embedded systems - CASES '12, 2012Co-Authors: Arun Raman, Jae W. Lee, David I. AugustAbstract:The embedded computing landscape is being transformed by three trends: growing demand for greater functionality and enriched user experience, increasing diversity and parallelism in the processing substrate, and an accelerating push for ever-greater energy efficiency. For programmers, these trends give rise to three challenges: writing code for a potentially heterogeneous architecture, extracting parallelism in software, and maximizing a multivariate (performance, power, energy, etc.) fitness function of user satisfaction which may vary with time. To meet these challenges, clarion calls have been issued for programmers to start writing software in new parallel Programming models. Fundamentally, however, these proposals detract programmers from delivering new features and enriched user experience in the shortest time possible. This paper proposes to attract embedded systems programmers to a vertically integrated approach, comprising extensions to the Sequential Programming model, a parallelizing compiler, and an optimizing run-time system, to enable them to tackle all three challenges.
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Revisiting the Sequential Programming Model for the Multicore Era
IEEE Micro, 2008Co-Authors: Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas B. Jablin, David I. AugustAbstract:Automatic parallelization has thus far not been successful at extracting scalable parallelism from general programs. An aggressive automatic thread extraction framework, coupled with natural extensions to the Sequential Programming model that allow for a range of legal outcomes rather than forcing programmers to define a single legal program outcome, will let programmers achieve the performance of parallel Programming via the simpler Sequential model.
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revisiting the Sequential Programming model for multi core
International Symposium on Microarchitecture, 2007Co-Authors: Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas B. Jablin, David I. AugustAbstract:Single-threaded Programming is already considered a complicated task. The move to multi-threaded Programming only increases the complexity and cost involved in software development due to rewriting legacy code, training of the programmer, increased debugging of the program, and ef- forts to avoid race conditions, deadlocks, and other prob- lems associated with parallel Programming. To address these costs, other approaches, such as automatic thread ex- traction, have been explored. Unfortunately, the amount of parallelism that has been automatically extracted is gener- ally insufficient to keep many cores busy. This paper argues that this lack of parallelism is not an intrinsic limitation of the Sequential Programming model, but rather occurs for two reasons. First, there exists no framework for automatic thread extraction that brings to- gether key existing state-of-the-art compiler and hardware techniques. This paper shows that such a framework can yield scalable parallelization on several SPEC CINT2000 benchmarks. Second, existing Sequential Programming lan- guages force programmers to define a single legal program outcome, rather than allowing for a range of legal out- comes. This paper shows that natural extensions to the se- quential Programming model enable parallelization for the remainder of the SPEC CINT2000 suite. Our experience demonstrates that, by changing only 60 source code lines, all of the C benchmarks in the SPEC CINT2000 suite were parallelizable by automatic thread extraction. This process, constrained by the limits of modern optimizing compilers, yielded a speedup of 454% on these applications.
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MICRO - Revisiting the Sequential Programming Model for Multi-Core
40th Annual IEEE ACM International Symposium on Microarchitecture (MICRO 2007), 2007Co-Authors: Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas B. Jablin, David I. AugustAbstract:Single-threaded Programming is already considered a complicated task. The move to multi-threaded Programming only increases the complexity and cost involved in software development due to rewriting legacy code, training of the programmer, increased debugging of the program, and ef- forts to avoid race conditions, deadlocks, and other prob- lems associated with parallel Programming. To address these costs, other approaches, such as automatic thread ex- traction, have been explored. Unfortunately, the amount of parallelism that has been automatically extracted is gener- ally insufficient to keep many cores busy. This paper argues that this lack of parallelism is not an intrinsic limitation of the Sequential Programming model, but rather occurs for two reasons. First, there exists no framework for automatic thread extraction that brings to- gether key existing state-of-the-art compiler and hardware techniques. This paper shows that such a framework can yield scalable parallelization on several SPEC CINT2000 benchmarks. Second, existing Sequential Programming lan- guages force programmers to define a single legal program outcome, rather than allowing for a range of legal out- comes. This paper shows that natural extensions to the se- quential Programming model enable parallelization for the remainder of the SPEC CINT2000 suite. Our experience demonstrates that, by changing only 60 source code lines, all of the C benchmarks in the SPEC CINT2000 suite were parallelizable by automatic thread extraction. This process, constrained by the limits of modern optimizing compilers, yielded a speedup of 454% on these applications.
Richard B Brown - One of the best experts on this subject based on the ideXlab platform.
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clock buffer and wire sizing using Sequential Programming
Design Automation Conference, 2006Co-Authors: Matthew R Guthaus, Dennis Sylvester, Richard B BrownAbstract:This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of Sequential Programming-based buffer/wire sizing is used. Then, a new formulation of clock skew minimization that uses quadratic Programming and considers sub-critical skews in addition to the most critical skews is presented. The quality of results are verified to be more robust using Monte Carlo simulations to account for process sensitivity. For the same power budget, the Sequential quadratic Programming (SQP) method has better expected skew, standard deviation, and overall CPU time on average.
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DAC - Clock buffer and wire sizing using Sequential Programming
Proceedings of the 43rd annual conference on Design automation - DAC '06, 2006Co-Authors: Matthew R Guthaus, Dennis Sylvester, Richard B BrownAbstract:This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of Sequential Programming-based buffer/wire sizing is used. Then, a new formulation of clock skew minimization that uses quadratic Programming and considers sub-critical skews in addition to the most critical skews is presented. The quality of results are verified to be more robust using Monte Carlo simulations to account for process sensitivity. For the same power budget, the Sequential quadratic Programming (SQP) method has better expected skew, standard deviation, and overall CPU time on average.
Michel Robert - One of the best experts on this subject based on the ideXlab platform.
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Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems
2007Co-Authors: Nicolas Saint-jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel RobertAbstract:Scalability of architecture, Programming model and task control management will be a major challenge for MP-SOC designs in the coming years. The contribution presented in this paper is HS-Scale, a hardware/software framework to study, define and experiment scalable solutions for next generation MP-SOC. The hardware architecture, H-Scale, is a homogeneous MP-SOC based on RISC processors, distributed memories and a globally asynchronous/locally synchronous network on chip. S-Scale is the software support to program H-Scale. It is a multithreaded Sequential Programming model with dedicated communication primitives handled at run-time by a simple operating system we developed. The hardware validations on FPGA and CMOS 90 nm technology and the experimental case studies on several applications (FIR, DES and MJPEG) demonstrate the scalability of our approach and draws interesting perspectives to automate task placement and duplication.
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HS-Scale: A Hardware-Software Scalable MP-SOC Architecture for Embedded Systems
2007Co-Authors: Nicolas Saint-jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel RobertAbstract:Scalability of architecture, Programming model and task control management will be a major challenge for MP-SOC designs in the coming years. The contribution presented in this paper is HS-Scale, a hardware/software framework to study, define and experiment scalable solutions for next generation MP-SOC. Our architecture, H-Scale, is a homogeneous MP-SOC based on RISC processors, distributed memories and an asynchronous network on chip. S-Scale is a multi-threaded Sequential Programming model with dedicated communication primitives handled at run-time by a simple Operating System we developed. The hardware validations and experiments on applications such as MJPEG and FIR filters demonstrate the scalability of our approach and draws interesting perspectives for distributed strategies of task control management.
Matthew J. Bridges - One of the best experts on this subject based on the ideXlab platform.
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Revisiting the Sequential Programming Model for the Multicore Era
IEEE Micro, 2008Co-Authors: Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas B. Jablin, David I. AugustAbstract:Automatic parallelization has thus far not been successful at extracting scalable parallelism from general programs. An aggressive automatic thread extraction framework, coupled with natural extensions to the Sequential Programming model that allow for a range of legal outcomes rather than forcing programmers to define a single legal program outcome, will let programmers achieve the performance of parallel Programming via the simpler Sequential model.
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revisiting the Sequential Programming model for multi core
International Symposium on Microarchitecture, 2007Co-Authors: Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas B. Jablin, David I. AugustAbstract:Single-threaded Programming is already considered a complicated task. The move to multi-threaded Programming only increases the complexity and cost involved in software development due to rewriting legacy code, training of the programmer, increased debugging of the program, and ef- forts to avoid race conditions, deadlocks, and other prob- lems associated with parallel Programming. To address these costs, other approaches, such as automatic thread ex- traction, have been explored. Unfortunately, the amount of parallelism that has been automatically extracted is gener- ally insufficient to keep many cores busy. This paper argues that this lack of parallelism is not an intrinsic limitation of the Sequential Programming model, but rather occurs for two reasons. First, there exists no framework for automatic thread extraction that brings to- gether key existing state-of-the-art compiler and hardware techniques. This paper shows that such a framework can yield scalable parallelization on several SPEC CINT2000 benchmarks. Second, existing Sequential Programming lan- guages force programmers to define a single legal program outcome, rather than allowing for a range of legal out- comes. This paper shows that natural extensions to the se- quential Programming model enable parallelization for the remainder of the SPEC CINT2000 suite. Our experience demonstrates that, by changing only 60 source code lines, all of the C benchmarks in the SPEC CINT2000 suite were parallelizable by automatic thread extraction. This process, constrained by the limits of modern optimizing compilers, yielded a speedup of 454% on these applications.
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MICRO - Revisiting the Sequential Programming Model for Multi-Core
40th Annual IEEE ACM International Symposium on Microarchitecture (MICRO 2007), 2007Co-Authors: Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas B. Jablin, David I. AugustAbstract:Single-threaded Programming is already considered a complicated task. The move to multi-threaded Programming only increases the complexity and cost involved in software development due to rewriting legacy code, training of the programmer, increased debugging of the program, and ef- forts to avoid race conditions, deadlocks, and other prob- lems associated with parallel Programming. To address these costs, other approaches, such as automatic thread ex- traction, have been explored. Unfortunately, the amount of parallelism that has been automatically extracted is gener- ally insufficient to keep many cores busy. This paper argues that this lack of parallelism is not an intrinsic limitation of the Sequential Programming model, but rather occurs for two reasons. First, there exists no framework for automatic thread extraction that brings to- gether key existing state-of-the-art compiler and hardware techniques. This paper shows that such a framework can yield scalable parallelization on several SPEC CINT2000 benchmarks. Second, existing Sequential Programming lan- guages force programmers to define a single legal program outcome, rather than allowing for a range of legal out- comes. This paper shows that natural extensions to the se- quential Programming model enable parallelization for the remainder of the SPEC CINT2000 suite. Our experience demonstrates that, by changing only 60 source code lines, all of the C benchmarks in the SPEC CINT2000 suite were parallelizable by automatic thread extraction. This process, constrained by the limits of modern optimizing compilers, yielded a speedup of 454% on these applications.
Matthew R Guthaus - One of the best experts on this subject based on the ideXlab platform.
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clock buffer and wire sizing using Sequential Programming
Design Automation Conference, 2006Co-Authors: Matthew R Guthaus, Dennis Sylvester, Richard B BrownAbstract:This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of Sequential Programming-based buffer/wire sizing is used. Then, a new formulation of clock skew minimization that uses quadratic Programming and considers sub-critical skews in addition to the most critical skews is presented. The quality of results are verified to be more robust using Monte Carlo simulations to account for process sensitivity. For the same power budget, the Sequential quadratic Programming (SQP) method has better expected skew, standard deviation, and overall CPU time on average.
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DAC - Clock buffer and wire sizing using Sequential Programming
Proceedings of the 43rd annual conference on Design automation - DAC '06, 2006Co-Authors: Matthew R Guthaus, Dennis Sylvester, Richard B BrownAbstract:This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of Sequential Programming-based buffer/wire sizing is used. Then, a new formulation of clock skew minimization that uses quadratic Programming and considers sub-critical skews in addition to the most critical skews is presented. The quality of results are verified to be more robust using Monte Carlo simulations to account for process sensitivity. For the same power budget, the Sequential quadratic Programming (SQP) method has better expected skew, standard deviation, and overall CPU time on average.