The Experts below are selected from a list of 102276 Experts worldwide ranked by ideXlab platform
Yusuf Leblebici - One of the best experts on this subject based on the ideXlab platform.
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design and modeling of Serial Data transceiver architecture by employing multi tone single sideband signaling scheme
IEEE Transactions on Circuits and Systems I-regular Papers, 2017Co-Authors: Gain Kim, Kiarash Gharibdoust, Thierry Barailler, Chen Cao, Yusuf LeblebiciAbstract:This paper presents the design and analysis of a Serial link transceiver (TRX) architecture employing analog multi-tone signaling for chip-to-chip communication. Multi-tone single-sideband signaling scheme is proposed in TRX architecture in order to optimize bandwidth requirements for each sub-channel and to improve signal-to-noise ratio by reducing inter-channel interferences (ICI) between neighboring sub-channels. System-level modeling results show that the proposed TRX architecture enables equalizer-free communication at 16 Gb/s over a lossy backplane channel that exhibits 22-dB attenuation at 8 GHz, while conventional non-return-to-zero signaling TRX necessitates a two-stage continuous-time linear equalizer. A channel frequency-response inversion scheme, the up/down-conversion mechanism of the TX/RX Data stream and the RX design considerations have been analyzed and investigated by architectural modeling.
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a fully digital spectrum shaping signaling for Serial Data transceiver with crosstalk and isi reduction property in multi drop memory interfaces
International Symposium on Circuits and Systems, 2016Co-Authors: Kiarash Gharibdoust, Gain Kim, Armin Tajalli, Yusuf LeblebiciAbstract:An efficient signaling scheme for Serial-Data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rather than analog/multi-tone approach, which can offer a very power-efficient and versatile silicon implementation. Moreover, the Xtalk induced noise can be fairly reduced by applying the proposed signaling, and the whole TRX can customize to the communication link trough digital calibration, while the aggregate Data rate is kept fixed.
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hybrid nrz multi tone Serial Data transceiver for multi drop memory interfaces
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Kiarash Gharibdoust, Armin Tajalli, Yusuf LeblebiciAbstract:A 7.5 Gb/s mixed NRZ/multi-tone (NRZ/MT) transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for an MDB channel with 45 dB loss at 2.5 GHz. The transmitted spectrum is composed of baseband (BB) and I/Q sub-bands with the ability to match the modulation frequency of the entire transceiver (TRX) with respect to the channel response over a ${{\pm 25\%}}$ range. A switched-capacitor-based mixer/filter is developed to efficiently down convert and equalize the I/Q sub-bands in the RX. The core size area is ${85\times 60\; \mu {\text{m}^2}}$ and ${150\times 60\; \mu {\text{m}^2}}$ for the TX and RX, respectively.
Tadahiko Sugibayashi - One of the best experts on this subject based on the ideXlab platform.
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noncomplimentary rewriting and Serial Data coding scheme for shared sense amplifier open bit line dram
IEEE Journal of Solid-state Circuits, 1999Co-Authors: Satoshi Utsugi, M Hanyu, Y Muramatsu, Tadahiko SugibayashiAbstract:A noncomplimentary rewriting scheme is proposed for open-bit-line DRAM's adopting a shared subsense amplifier. The scheme can theoretically cancel inter-bit-line coupling noise down to zero. In order to suppress the peak in unselected word line noise, a Serial-Data coding scheme was also developed, This scheme can reduce unselected word-line noise by at least 50%.
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non complimentary rewriting and Serial Data coding scheme for shared sense amplifier open bit line drams
Symposium on VLSI Circuits, 1998Co-Authors: Satoshi Utsugi, M Hanyu, Y Muramatsu, Tadahiko SugibayashiAbstract:A non-complimentary rewriting scheme is proposed for open-bit-line DRAMs adopting shared-sub-sense amplifier. The scheme can theoretically cancel inter-bit-line coupling noise down to zero. In order to suppress the peak in word-line noise, a Serial-Data coding scheme was also developed. This scheme can reduce word-line noise to at least 50%. These two circuits were applied to an experimental 1 Gb DRAM using 0.22 /spl mu/m CMOS process technology for file applications.
Kiarash Gharibdoust - One of the best experts on this subject based on the ideXlab platform.
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design and modeling of Serial Data transceiver architecture by employing multi tone single sideband signaling scheme
IEEE Transactions on Circuits and Systems I-regular Papers, 2017Co-Authors: Gain Kim, Kiarash Gharibdoust, Thierry Barailler, Chen Cao, Yusuf LeblebiciAbstract:This paper presents the design and analysis of a Serial link transceiver (TRX) architecture employing analog multi-tone signaling for chip-to-chip communication. Multi-tone single-sideband signaling scheme is proposed in TRX architecture in order to optimize bandwidth requirements for each sub-channel and to improve signal-to-noise ratio by reducing inter-channel interferences (ICI) between neighboring sub-channels. System-level modeling results show that the proposed TRX architecture enables equalizer-free communication at 16 Gb/s over a lossy backplane channel that exhibits 22-dB attenuation at 8 GHz, while conventional non-return-to-zero signaling TRX necessitates a two-stage continuous-time linear equalizer. A channel frequency-response inversion scheme, the up/down-conversion mechanism of the TX/RX Data stream and the RX design considerations have been analyzed and investigated by architectural modeling.
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a digital spectrum shaping signaling Serial Data transceiver with crosstalk and isi reduction property in multidrop interfaces
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2016Co-Authors: Gain Kim, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici ComAbstract:A transceiver (TRX) architecture employing a spectrum shaping signaling scheme is proposed, which can significantly reduce intersymbol interference and crosstalk in multidrop interfaces. The proposed TRX architecture relies on digital implementation rather than an analog/multitone approach, which can offer a power-efficient and versatile silicon implementation. Moreover, the crosstalk-induced noise can be reduced by applying the spectrum shaping signaling, and the whole TRX can be customized to the communication link by digital calibration while the aggregate Data rate is kept fixed.
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a fully digital spectrum shaping signaling for Serial Data transceiver with crosstalk and isi reduction property in multi drop memory interfaces
International Symposium on Circuits and Systems, 2016Co-Authors: Kiarash Gharibdoust, Gain Kim, Armin Tajalli, Yusuf LeblebiciAbstract:An efficient signaling scheme for Serial-Data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rather than analog/multi-tone approach, which can offer a very power-efficient and versatile silicon implementation. Moreover, the Xtalk induced noise can be fairly reduced by applying the proposed signaling, and the whole TRX can customize to the communication link trough digital calibration, while the aggregate Data rate is kept fixed.
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hybrid nrz multi tone Serial Data transceiver for multi drop memory interfaces
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Kiarash Gharibdoust, Armin Tajalli, Yusuf LeblebiciAbstract:A 7.5 Gb/s mixed NRZ/multi-tone (NRZ/MT) transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for an MDB channel with 45 dB loss at 2.5 GHz. The transmitted spectrum is composed of baseband (BB) and I/Q sub-bands with the ability to match the modulation frequency of the entire transceiver (TRX) with respect to the channel response over a ${{\pm 25\%}}$ range. A switched-capacitor-based mixer/filter is developed to efficiently down convert and equalize the I/Q sub-bands in the RX. The core size area is ${85\times 60\; \mu {\text{m}^2}}$ and ${150\times 60\; \mu {\text{m}^2}}$ for the TX and RX, respectively.
Leif Katsuo Oxenlowe - One of the best experts on this subject based on the ideXlab platform.
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algaas on insulator nanowire with 750 nm fwm bandwidth 9 db cw conversion efficiency and ultrafast operation enabling record tbaud wavelength conversion
Optical Fiber Communication Conference, 2015Co-Authors: Luisa Ottaviano, Leif Katsuo Oxenlowe, Elizaveta Semenova, Dragana Vukovic, Kresten YvindAbstract:We present an AlGaAs-on-insulator platform for integrated nonlinear photonics. We demonstrate the highest reported conversion efficiency/length/pump-power, ultra-broadband four-wave mixing, and first-ever wavelength conversion of 1.28-Tbaud Serial Data signals in a 3-mm long dispersion-engineered AlGaAs nano-waveguide.
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silicon photonics for signal processing of tbit s Serial Data signals
IEEE Journal of Selected Topics in Quantum Electronics, 2012Co-Authors: Leif Katsuo Oxenlowe, Jørn Märcher Hvam, Kresten Yvind, Michael Galili, H C H Mulvad, A T Clausen, P JeppesenAbstract:In this paper, we describe our recent work on signal processing of terabit per second optical Serial Data signals using pure silicon waveguides. We employ nonlinear optical signal processing in nanoengineered silicon waveguides to perform demultiplexing and optical waveform sampling of 1.28-Tbit/s Data signals as well as wavelength conversion of up to 320-Gbit/s Data signals. We demonstrate that the silicon waveguides are equally useful for amplitude and phase-modulated Data signals.
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optical waveform sampling and error free demultiplexing of 1 28 tb s Serial Data in a nanoengineered silicon waveguide
Journal of Lightwave Technology, 2011Co-Authors: H. Ji, Jørn Märcher Hvam, Kresten Yvind, Leif Katsuo Oxenlowe, Michael Galili, Minhao Pu, Hao Hu, Palle JeppesenAbstract:This paper presents the experimental demonstrations of using a pure nanoengineered silicon waveguide for 1.28 Tb/s Serial Data optical waveform sampling and 1.28 Tb/s-10 Gb/s error-free demultiplexing. The 330-fs pulses are resolved in each 780-fs time slot in waveform sampling. Error-free operation is achieved in the 1.28 Tb/s-10 Gb/s demultiplexing.
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optical waveform sampling and error free demultiplexing of 1 28 tbit s Serial Data in a silicon nanowire
Optical Fiber Communication Conference, 2010Co-Authors: Michael Galili, Jørn Märcher Hvam, Kresten Yvind, Leif Katsuo Oxenlowe, P JeppesenAbstract:We experimentally demonstrate 640 Gbit/s and 1.28 Tbit/s Serial Data optical waveform sampling and 640-to-10 Gbit/s and 1.28 Tbit/s-to-10 Gbit/s error-free demultiplexing using four-wave mixing in a 300nm×450nm×5mm silicon nanowire.
Satoshi Utsugi - One of the best experts on this subject based on the ideXlab platform.
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noncomplimentary rewriting and Serial Data coding scheme for shared sense amplifier open bit line dram
IEEE Journal of Solid-state Circuits, 1999Co-Authors: Satoshi Utsugi, M Hanyu, Y Muramatsu, Tadahiko SugibayashiAbstract:A noncomplimentary rewriting scheme is proposed for open-bit-line DRAM's adopting a shared subsense amplifier. The scheme can theoretically cancel inter-bit-line coupling noise down to zero. In order to suppress the peak in unselected word line noise, a Serial-Data coding scheme was also developed, This scheme can reduce unselected word-line noise by at least 50%.
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non complimentary rewriting and Serial Data coding scheme for shared sense amplifier open bit line drams
Symposium on VLSI Circuits, 1998Co-Authors: Satoshi Utsugi, M Hanyu, Y Muramatsu, Tadahiko SugibayashiAbstract:A non-complimentary rewriting scheme is proposed for open-bit-line DRAMs adopting shared-sub-sense amplifier. The scheme can theoretically cancel inter-bit-line coupling noise down to zero. In order to suppress the peak in word-line noise, a Serial-Data coding scheme was also developed. This scheme can reduce word-line noise to at least 50%. These two circuits were applied to an experimental 1 Gb DRAM using 0.22 /spl mu/m CMOS process technology for file applications.
