The Experts below are selected from a list of 3243 Experts worldwide ranked by ideXlab platform
Yukihiro Fujimoto - One of the best experts on this subject based on the ideXlab platform.
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a current controlled latch Sense Amplifier and a static power saving input buffer for low power architecture
IEEE Journal of Solid-state Circuits, 1993Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro FujimotoAbstract:Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch Sense Amplifier that reduces the power dissipation by stopping Sense current automatically. This Sense Amplifier reduces power without degrading access time compared with the conventional current-mirror Sense Amplifier. The other is a static power-saving input buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM. >
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a current mode latch Sense Amplifier and a static power saving input buffer for low power architecture
Symposium on VLSI Circuits, 1992Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto, O WatanabeAbstract:Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch Sense Amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror Sense Amplifier operation. The other is a static power saving input buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch Sense Amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit. >
T Kobayashi - One of the best experts on this subject based on the ideXlab platform.
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a current controlled latch Sense Amplifier and a static power saving input buffer for low power architecture
IEEE Journal of Solid-state Circuits, 1993Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro FujimotoAbstract:Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch Sense Amplifier that reduces the power dissipation by stopping Sense current automatically. This Sense Amplifier reduces power without degrading access time compared with the conventional current-mirror Sense Amplifier. The other is a static power-saving input buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM. >
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a current mode latch Sense Amplifier and a static power saving input buffer for low power architecture
Symposium on VLSI Circuits, 1992Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto, O WatanabeAbstract:Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch Sense Amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror Sense Amplifier operation. The other is a static power saving input buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch Sense Amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit. >
Doris Schmittlandsiedel - One of the best experts on this subject based on the ideXlab platform.
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yield and speed optimization of a latch type voltage Sense Amplifier
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Bernhard Wicht, T Nirschl, Doris SchmittlandsiedelAbstract:A quantitative yield analysis of a latch-type voltage Sense Amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD/ is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.
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a simple low voltage current Sense Amplifier with switchable input transistor
European Solid-State Circuits Conference, 2001Co-Authors: Bernhard Wicht, Doris Schmittlandsiedel, Steffen PaulAbstract:A simple SRAM current Sense Amplifier with common gate input stage is presented. Instead of keeping the gate at constant potential it is controlled by the select signal of the bit line multiplexer (MUX). If the transistor is turned on it maintains a low input resistance while the off-state is used for multiplexing and power down. Experimental results in 0.18µm 1.8V CMOS show that the circuit is superior to conventional voltage sensing. It is shown that for supply voltages below IV where the driving cell currents become very small, only current sensing is capable of fast reading. For a 0.12µm technology the simulated lower supply voltage limit of the proposed circuit is as low as 0.4V.
Jaeyoon Sim - One of the best experts on this subject based on the ideXlab platform.
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current mode transceiver for silicon interposer channel
IEEE Journal of Solid-state Circuits, 2014Co-Authors: Seunghun Lee, Seonkyoo Lee, Byungsub Kim, Hongjune Park, Jaeyoon SimAbstract:An energy-efficient 3 Gb/s current-mode interface scheme is proposed for on-chip global interconnects and silicon interposer channels. The transceiver core consists of an open-drain transmitter with one-tap pre-emphasis and a current Sense Amplifier load as the receiver. The current Sense Amplifier load is formed by stacking a PMOS diode stage and a cross-coupled NMOS stage, providing an optimum current-mode receiver without any bias current. The proposed scheme is verified with two cases of transceivers implemented in 65 nm CMOS. A 10 mm point-to-point data-only channel shows an energy efficiency of 9.5 fJ/b/mm, and a 20 mm four-drop source-synchronous link achieves 29.4 fJ/b/mm including clock and data channels.
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a 1 8 v 128 mb mobile dram with double boosting pump hybrid current Sense Amplifier and dual referenced adjustment scheme for temperature sensor
IEEE Journal of Solid-state Circuits, 2003Co-Authors: Jaeyoon Sim, Hongil Yoon, Kichul Chun, Hyunseok Lee, Sangpyo Hong, Kyuchan Lee, Jeihwan Yoo, Dongil Seo, Sooin ChoAbstract:To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb SDRAM was implemented with a 0.15-/spl mu/m technology. To achieve an ideal 33% efficiency, the double boosting pump uses two capacitor's series connection at pumping phase, while they are precharged in parallel. The hybrid folded current Sense Amplifier together with a novel replica inverter connection improved power and speed performances. Also, a dual-referenced adjustment scheme for a temperature sensor was proposed to allow a very high accuracy in tuning. Without loss in productivity, the implemented dual-referenced searching technique achieved tuning error of less than /spl plusmn/2.5/spl deg/C.
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double boosting pump hybrid current Sense Amplifier and binary weighted temperature sensor adjustment schemes for 1 8v 128mb mobile drams
Symposium on VLSI Circuits, 2002Co-Authors: Jaeyoon Sim, Hongil Yoon, Kichul Chun, Hyunseok Lee, Sangpyo Hong, Sooyoung Kim, Minsoo Kim, Kyuchan Lee, Jeihwan Yoo, Dongil SeoAbstract:A 1.8V 128Mb SDRAM is implemented for low current mobile applications with a 0.15/spl mu/m technology. The double boosting pump and hybrid current Sense Amplifier schemes are optimized for the low voltage regime with high pumping efficiency and stable I-to-V gain, respectively. A temperature sensor together with the binary weighted adjustment technique allow a very accurate implementation without loss in productivity.
Jan M Rabaey - One of the best experts on this subject based on the ideXlab platform.
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asynchronous computing in Sense Amplifier based pass transistor logic
IEEE Transactions on Very Large Scale Integration Systems, 2009Co-Authors: Tsungte Liu, Louis P Alarcon, M D Pierson, Jan M RabaeyAbstract:This paper presents the design and implementation of a low-energy asynchronous logic topology using Sense Amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. We show two different self-timed approaches: 1) the bundled data and 2) the dual-rail handshaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches in 90-nm CMOS.
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asynchronous computing in Sense Amplifier based pass transistor logic
IEEE International Symposium on Asynchronous Circuits and Systems, 2008Co-Authors: Tsungte Liu, Louis P Alarcon, M D Pierson, Jan M RabaeyAbstract:This paper presents the design and implementation of a low energy asynchronous logic architecture using Sense Amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low leakage pass transistors and low supply voltage. The introduction of asynchronous operation in SAPTL further improves energy-delay performance and reliability without increasing hardware complexity. We show two different self-timed approaches using a bundled-data and a dual-rail handshaking protocol, respectively. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled-data self-timed approaches.
