The Experts below are selected from a list of 177 Experts worldwide ranked by ideXlab platform
Ronald Nick Kalla - One of the best experts on this subject based on the ideXlab platform.
-
IBM POWER7 multicore Server Processor
Journal of Reproduction and Development, 2011Co-Authors: Balaram Sinharoy, Ronald Nick Kalla, William J. Starke, Robert Alan Cargnoni, J. A. Van Norstrand, Bruce Joseph Ronchetti, Jeffrey A. Stuecheli, Jentje Leenstra, Guy Lynn GuthrieAbstract:The IBM POWER® Processor is the dominant reduced instruction set computing microProcessor in the world today, with a rich history of implementation and innovation over the last 20 years. In this paper, we describe the key features of the POWER7® Processor chip. On the chip is an eight-core Processor, with each core capable of four-way simultaneous multithreaded operation. Fabricated in IBM's 45-nm silicon-on-insulator (SOI) technology with 11 levels of metal, the chip contains more than one billion transistors. The Processor core and caches are significantly enhanced to boost the performance of both single-threaded response-time-oriented, as well as multithreaded, throughput-oriented applications. The memory subsystem contains three levels of on-chip cache, with SOI embedded dynamic random access memory (DRAM) devices used as the last level of cache. A new memory interface using buffered double-data-rate-three DRAM and improvements in reliability, availability, and serviceability are discussed
-
power7 a highly parallel scalable multi core high end Server Processor
IEEE Journal of Solid-state Circuits, 2011Co-Authors: Dieter Wendel, Ronald Nick Kalla, Robert Alan Cargnoni, J Warnock, Sam Gatshang Chu, Joachim Gerhard Clabes, Daniel M Dreps, David A Hrusecky, Joshua Friedrich, Saiful IslamAbstract:This paper gives an overview of the latest member of the POWER™ Processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 567 mm die, employing 1.2B transistors in a 45 nm CMOS SOI technology with 11 layers of low-k copper wiring. The technology features deep trench capacitors which are used to build a 32 MB embedded DRAM L3 based on a 0.067 m DRAM cell. The functionally equivalent chip transistor count would have been over 2.7B if the L3 had been implemented with a conventional 6 transistor SRAM cell. (A detailed paper about the eDRAM implementation will be given in a separate paper of this Journal). Deep trench capacitors are also used to reduce on-chip voltage island supply noise. This paper describes the organization of the design and the features of the Processor core, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs. The final section describes the details of the clocked storage elements, including special features for test, debug, and chip frequency tuning.
-
the implementation of power7 tm a highly parallel and scalable multi core high end Server Processor
International Solid-State Circuits Conference, 2010Co-Authors: Dieter Wendel, Balaram Sinharoy, Ronald Nick Kalla, William J. Starke, Joshua Friedrich, Roland Frech, Robert Cargoni, Joachim Clables, James Allan Kahle, Scott A TaylorAbstract:The next Processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.
-
ISSCC - The implementation of POWER7 TM : A highly parallel and scalable multi-core high-end Server Processor
2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010Co-Authors: Dieter Wendel, Balaram Sinharoy, Ronald Nick Kalla, William J. Starke, Joshua Friedrich, Roland Frech, Robert Cargoni, Joachim Clables, James Allan Kahle, Scott A TaylorAbstract:The next Processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.
-
POWER7: IBM's next generation Server Processor
2009 IEEE Hot Chips 21 Symposium (HCS), 2009Co-Authors: Ronald Nick Kalla, Balaram SinharoyAbstract:Power Systems™ continue strong ■ 7th Generation Power chip: ■ Balanced Multi-Core design ■ EDRAM technology ■ SMT4 ■ Greater then 4X performance in same power envelope as previous generation ■ Scales to 32 socket, 1024 threads balanced system ■ Building block for peta-scale PERCS project POWER7 Systems Running in Lab ▪ AIX®, IBM i, Linux® all operational
Dieter Wendel - One of the best experts on this subject based on the ideXlab platform.
-
power7 a highly parallel scalable multi core high end Server Processor
IEEE Journal of Solid-state Circuits, 2011Co-Authors: Dieter Wendel, Ronald Nick Kalla, Robert Alan Cargnoni, J Warnock, Sam Gatshang Chu, Joachim Gerhard Clabes, Daniel M Dreps, David A Hrusecky, Joshua Friedrich, Saiful IslamAbstract:This paper gives an overview of the latest member of the POWER™ Processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 567 mm die, employing 1.2B transistors in a 45 nm CMOS SOI technology with 11 layers of low-k copper wiring. The technology features deep trench capacitors which are used to build a 32 MB embedded DRAM L3 based on a 0.067 m DRAM cell. The functionally equivalent chip transistor count would have been over 2.7B if the L3 had been implemented with a conventional 6 transistor SRAM cell. (A detailed paper about the eDRAM implementation will be given in a separate paper of this Journal). Deep trench capacitors are also used to reduce on-chip voltage island supply noise. This paper describes the organization of the design and the features of the Processor core, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs. The final section describes the details of the clocked storage elements, including special features for test, debug, and chip frequency tuning.
-
the implementation of power7 tm a highly parallel and scalable multi core high end Server Processor
International Solid-State Circuits Conference, 2010Co-Authors: Dieter Wendel, Balaram Sinharoy, Ronald Nick Kalla, William J. Starke, Joshua Friedrich, Roland Frech, Robert Cargoni, Joachim Clables, James Allan Kahle, Scott A TaylorAbstract:The next Processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.
-
ISSCC - The implementation of POWER7 TM : A highly parallel and scalable multi-core high-end Server Processor
2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010Co-Authors: Dieter Wendel, Balaram Sinharoy, Ronald Nick Kalla, William J. Starke, Joshua Friedrich, Roland Frech, Robert Cargoni, Joachim Clables, James Allan Kahle, Scott A TaylorAbstract:The next Processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.
Saiful Islam - One of the best experts on this subject based on the ideXlab platform.
-
power7 a highly parallel scalable multi core high end Server Processor
IEEE Journal of Solid-state Circuits, 2011Co-Authors: Dieter Wendel, Ronald Nick Kalla, Robert Alan Cargnoni, J Warnock, Sam Gatshang Chu, Joachim Gerhard Clabes, Daniel M Dreps, David A Hrusecky, Joshua Friedrich, Saiful IslamAbstract:This paper gives an overview of the latest member of the POWER™ Processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 567 mm die, employing 1.2B transistors in a 45 nm CMOS SOI technology with 11 layers of low-k copper wiring. The technology features deep trench capacitors which are used to build a 32 MB embedded DRAM L3 based on a 0.067 m DRAM cell. The functionally equivalent chip transistor count would have been over 2.7B if the L3 had been implemented with a conventional 6 transistor SRAM cell. (A detailed paper about the eDRAM implementation will be given in a separate paper of this Journal). Deep trench capacitors are also used to reduce on-chip voltage island supply noise. This paper describes the organization of the design and the features of the Processor core, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs. The final section describes the details of the clocked storage elements, including special features for test, debug, and chip frequency tuning.
Julien Leduc - One of the best experts on this subject based on the ideXlab platform.
-
Evaluation of the Intel Sandy Bridge-EP Server Processor
2012Co-Authors: Sverre Jarp, Alfio Lazzaro, Andrzej Nowak, Julien LeducAbstract:In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” Processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these Processors are “Xeon E5-2600 Processor series” and “Xeon 5600 Processor series”, respectively. Both Processors are produced in a 32nm process, and both platforms are dual-socket Servers. Multiple benchmarks were used to get a good understanding of the performance of the new Processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events.
-
Evaluation of the Intel 4 socket Sandy Bridge-EP Server Processor
2012Co-Authors: Sverre Jarp, Alfio Lazzaro, Andrzej Nowak, Liviu Valsan, Julien LeducAbstract:In this paper we report on a set of benchmark results obtained by CERN openlab when comparing a 32-core, quad socket, “Sandy Bridge-EP” Server with a 16-core, dual socket, “Sandy Bridge-EP” Server and a 40-core, quad socket Server using Intel’s previous microarchitecture, the “Westmere-EX”. The Intel marketing names for the corresponding Processors are the “Xeon E5-4600 Processor series”, “Xeon E5-2600 Processor series” and “Xeon E7-4800 Processor series”, respectively. All three Processors are produced using a 32 nm process. Multiple benchmarks were used to get a good understanding of the performance of each Processor. We used both industry-standard benchmarks, such as SPEC CPU2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events.
-
Evaluation of the Intel Westmere-EP Server Processor
2010Co-Authors: Sverre Jarp, Alfio Lazzaro, Julien Leduc, Andrzej NowakAbstract:In summary, we see good scaling with the core count. We observed a very appreciable throughput increase of up to 61% when using the in-house benchmarks, compared to the previous Processor generation. Our variant of the SPEC benchmark rate, “HEPSPEC06”, gives 32% more throughput. HEPSPEC per watt is measured to improve by up to 23% which is less than the improvement when going from Harpertown to Nehalem (36%). Benefits of SMT were seen to be of similar significance as in the previous Processor generation.
Balaram Sinharoy - One of the best experts on this subject based on the ideXlab platform.
-
IBM POWER7 multicore Server Processor
Journal of Reproduction and Development, 2011Co-Authors: Balaram Sinharoy, Ronald Nick Kalla, William J. Starke, Robert Alan Cargnoni, J. A. Van Norstrand, Bruce Joseph Ronchetti, Jeffrey A. Stuecheli, Jentje Leenstra, Guy Lynn GuthrieAbstract:The IBM POWER® Processor is the dominant reduced instruction set computing microProcessor in the world today, with a rich history of implementation and innovation over the last 20 years. In this paper, we describe the key features of the POWER7® Processor chip. On the chip is an eight-core Processor, with each core capable of four-way simultaneous multithreaded operation. Fabricated in IBM's 45-nm silicon-on-insulator (SOI) technology with 11 levels of metal, the chip contains more than one billion transistors. The Processor core and caches are significantly enhanced to boost the performance of both single-threaded response-time-oriented, as well as multithreaded, throughput-oriented applications. The memory subsystem contains three levels of on-chip cache, with SOI embedded dynamic random access memory (DRAM) devices used as the last level of cache. A new memory interface using buffered double-data-rate-three DRAM and improvements in reliability, availability, and serviceability are discussed
-
the implementation of power7 tm a highly parallel and scalable multi core high end Server Processor
International Solid-State Circuits Conference, 2010Co-Authors: Dieter Wendel, Balaram Sinharoy, Ronald Nick Kalla, William J. Starke, Joshua Friedrich, Roland Frech, Robert Cargoni, Joachim Clables, James Allan Kahle, Scott A TaylorAbstract:The next Processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.
-
Power7: IBM's Next-Generation Server Processor
IEEE Micro, 2010Co-Authors: Ron Kalla, Balaram Sinharoy, William J. Starke, Michael Stephen FloydAbstract:The Power7 is IBM's first eight-core Processor, with each core capable of four-way simultaneous-multithreading operation. Its key architectural features include an advanced memory hierarchy with three levels of on-chip cache; embedded-DRAM devices used in the highest level of the cache; and a new memory interface. This balanced multicore design scales from 1 to 32 sockets in commercial and scientific environments.
-
ISSCC - The implementation of POWER7 TM : A highly parallel and scalable multi-core high-end Server Processor
2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010Co-Authors: Dieter Wendel, Balaram Sinharoy, Ronald Nick Kalla, William J. Starke, Joshua Friedrich, Roland Frech, Robert Cargoni, Joachim Clables, James Allan Kahle, Scott A TaylorAbstract:The next Processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.
-
POWER7: IBM's next generation Server Processor
2009 IEEE Hot Chips 21 Symposium (HCS), 2009Co-Authors: Ronald Nick Kalla, Balaram SinharoyAbstract:Power Systems™ continue strong ■ 7th Generation Power chip: ■ Balanced Multi-Core design ■ EDRAM technology ■ SMT4 ■ Greater then 4X performance in same power envelope as previous generation ■ Scales to 32 socket, 1024 threads balanced system ■ Building block for peta-scale PERCS project POWER7 Systems Running in Lab ▪ AIX®, IBM i, Linux® all operational
