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Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.
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reducing set associative Cache energy via way prediction and selective direct mapping
International Symposium on Microarchitecture, 2001Co-Authors: Michael D Powell, Amit Agarwal, T N Vijaykumar, Babak Falsafi, Kaushik RoyAbstract:Set-Associative Caches achieve low miss rates for typical applications but result in significant energy dissipation. Set-Associative Caches minimize access time by probing all the data ways in parallel with the tag lookup, although the output of only the matching way is used. The energy spent accessing the other ways is wasted Eliminating the wasted energy by performing the data lookup sequentially following the tag lookup substantially increases Cache access time, and is unacceptable for high-performance L1 Caches. In this paper, we apply two previously-proposed techniques, way-prediction and selective direct-mapping, to reducing L1 Cache dynamic energy while maintaining high performance. The techniques predict the matching way and probe only the predicted way and not all the ways, achieving energy savings. While these techniques were originally proposed to improve Set-Associative Cache access times, this is the first paper to apply them to reducing Cache energy. We evaluate the effectiveness of these techniques in reducing L1 d-Cache, L1 i-Cache, and overall processor energy. Using these techniques, our Caches achieve the energy-delay of sequential access while maintaining the performance of parallel access. Relative to parallel access L1 i- and d-Caches, the techniques achieve overall processor energy-delay reduction of 8%, while perfect way-prediction with no performance degradation achieves 10% reduction. The performance degradation of the techniques is less than 3%, compared to an aggressive,.1-cycle, 4-way, parallel access Cache.
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MICRO - Reducing Set-Associative Cache energy via way-prediction and selective direct-mapping
Proceedings. 34th ACM IEEE International Symposium on Microarchitecture. MICRO-34, 1Co-Authors: Michael D Powell, Amit Agarwal, T N Vijaykumar, Babak Falsafi, Kaushik RoyAbstract:Set-Associative Caches achieve low miss rates for typical applications but result in significant energy dissipation. Set-Associative Caches minimize access time by probing all the data ways in parallel with the tag lookup, although the output of only the matching way is used. The energy spent accessing the other ways is wasted Eliminating the wasted energy by performing the data lookup sequentially following the tag lookup substantially increases Cache access time, and is unacceptable for high-performance L1 Caches. In this paper, we apply two previously-proposed techniques, way-prediction and selective direct-mapping, to reducing L1 Cache dynamic energy while maintaining high performance. The techniques predict the matching way and probe only the predicted way and not all the ways, achieving energy savings. While these techniques were originally proposed to improve Set-Associative Cache access times, this is the first paper to apply them to reducing Cache energy. We evaluate the effectiveness of these techniques in reducing L1 d-Cache, L1 i-Cache, and overall processor energy. Using these techniques, our Caches achieve the energy-delay of sequential access while maintaining the performance of parallel access. Relative to parallel access L1 i- and d-Caches, the techniques achieve overall processor energy-delay reduction of 8%, while perfect way-prediction with no performance degradation achieves 10% reduction. The performance degradation of the techniques is less than 3%, compared to an aggressive,.1-cycle, 4-way, parallel access Cache.
S. Subha - One of the best experts on this subject based on the ideXlab platform.
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A Power Saving Set Associative Cache Model
Indian Journal of Science and Technology, 2016Co-Authors: S. SubhaAbstract:Background/Objectives: Placing conflict Cache lines in alternate set is proposed for set associative Caches in literature. The conflicting lines are placed in one alternate set for each set. Methods/Statistical Analysis: This paper proposes architecture to place conflicting lines in set with maximum vacant ways in set associative Caches. The model introduces one register per Cache way with number of bits equal to number of Cache sets. A sequential circuit using the register enables the Cache ways of any set. The unoccupied ways are disabled. The proposed model is simulated with SPEC2K benchmarks. The power consumption is calculated using Quartus 2 tool and verilog code. Findings: An average improvement in power consumption of 68% for benchmarks with partial filled Cache ways is observed with average memory access degradation of about 4.86%. A performance degradation in average memory access time of about 34% compared with direct mapped Cache system and 3% compared with random placement algorithm is observed for the proposed system. The proposed model is for power consumption as is validated from the findings. The proposed model can be adapted for set associative Caches to improve power consumption. Applications/Improvements: A model with optimal operational Cache sets with methods to decrease power dissipation of sequential circuits, low power techniques for digital circuits can be used to improve the power consumption
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A reconfigurable Cache architecture
2014 International Conference on High Performance Computing and Applications (ICHPCA), 2014Co-Authors: S. SubhaAbstract:All Cache ways in w-way set associative Cache are enabled during operation. This paper proposes an architecture to enable the occupied ways of w-way set associative Cache. A variable set Cache architecture is assumed. The proposed model introduces sequential component in Cache circuit to enable the selected ways. The ways are put in off mode initially. The proposed model is simulated with SPEC2K benchmarks. The proposed model shows average power saving of 6.7% for level one Cache of 2048 sets with associativities 8, 16, 32, level two Cache size of 4096 sets with associativities 16, 32, 64 respectively in two level inclusive Cache. The proposed model shows average power improvement of 4.7% for level one Cache of 4096 sets with associativities 8, 16, 32, level two Cache of 8192 sets with associativities of 16, 32, 64 respectively. The average memory access time is comparable in all configurations with the traditional model.
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An Energy Efficient Set Associative Cache Algorithm
International Journal of Computer Applications, 2013Co-Authors: S. SubhaAbstract:associative Caches have fixed ways. Entire Cache is enabled during Cache operation. This paper proposes Cache architecture mapping Cache line to fixed Cache way of mapped set. The address is mapped to set as in conventional set associative Cache. The tag value of the mapped line is divided into blocks of size of number of Cache ways. The average of maximum and minimum frequency of this division is the mapped way. The proposed model is simulated with SPEC2K benchmarks. The average memory access time degradation of 3.8% is seen over traditional set associative Cache. The energy saving of 49% is observed in proposed model.
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A Cache architecture
2013 15th International Conference on Advanced Computing Technologies (ICACT), 2013Co-Authors: S. SubhaAbstract:Caches are widely used in computers. This paper proposes an algorithm to increase the number of Cache ways in w-way set associative Cache to maximum of 2w ways. The addresses resulting in conflict miss to a set are placed in other_set. The other set is chosen as the set with maximum vacant Cache ways. The least recently used Cache way is replaced in case of no vacant Cache ways in the other_set. An owner vector indicates a line to belong to a set. The proposed model is simulated using SPEC2K benchmarks. A performance improvement of 2.5% in average memory access time is observed over traditional set associative Cache. The performance is comparable to 2w-way set associative Cache for chosen parameters. The energy consumption implementing tag Cache model showed an increase of about 13% over traditional set associative Cache of same size.
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An algorithm for variable Cache ways
2013 International Conference on Advances in Technology and Engineering (ICATE), 2013Co-Authors: S. SubhaAbstract:This paper proposed an algorithm for varying Cache ways in set associative Cache. The ways of the mapped Cache set are extended to half of the ways of adjacent sets in this model. A set is thus viewed as growing in both ways. If a way is free in this extended model, the line is placed in the way. An owner vector indicates the set owner ship of the way. If all the ways are full, the least recently used way of the mapped set is replaced. The proposed model adopts tag Cache model proposed in literature. The proposed model is simulated with SPEC2000 benchmarks. An improvement of 5% in average memory access time over traditional w-way set associative model and 3% over 2w-way set associative Cache model for chosen parameters is observed. The energy consumed in the proposed model is comparable to the traditional set associative Cache of same size.
Chuanjun Zhang - One of the best experts on this subject based on the ideXlab platform.
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4.3 A Way-Halting Cache for Low-Energy High-Performance Systems
2013Co-Authors: Chuanjun Zhang, Frank Vahid, Jun Yang, Walid NajjarAbstract:Caches contribute to much of a microprocessor system's power and energy consumption. We have developed a new Cache architecture, called a way-halting Cache, that reduces energy while imposing no performance overhead. Our way-halting Cache is a four-way Set-Associative Cache that stores the four lowest-order bits of all ways ’ tags into a fully associative memory, which we call the halt tag array. The lookup in the halt tag array is done in parallel with, and is no slower than, the set-index decoding. The halt tag array pre-determines which tags cannot match due to their low-order four bits mismatching. Further accesses to ways with known mismatching tags are then halted, thus saving power. Our halt tag array has an additional feature of using static logic only, rather than dynamic logic used in highly associative Caches. We provide data from experiments on 17 benchmarks drawn from MediaBench and Spec 2000, based on our layouts in 0.18 micron CMOS technology. On average, 55 % savings of memory-access related energy were obtained over a conventional four-way Set-Associative Cache. We show that energy savings are greater than previous methods, and nearly twice that of highly-associative Caches, while imposing no performance overhead and only 2 % Cache area overhead
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an efficient direct mapped instruction Cache for application specific embedded systems
International Conference on Hardware Software Codesign and System Synthesis, 2005Co-Authors: Chuanjun ZhangAbstract:Caches may consume half of a microprocessor's total power and Cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing Cache power consumption and reducing Cache misses are important to reduce total energy consumption of embedded systems. Direct mapped Caches consume much less power than that of same sized set associative Caches but with a poor hit rate on average. Through experiments, we observe that memory space of direct mapped instruction Caches is not used efficiently in most embedded applications. We design an efficient Cache - a configurable instruction Cache that can be tuned to utilize the Cache sets efficiently for a particular application such that Cache memory is exploited more efficiently by index remapping. Experiments on 11 benchmarks drawn from Mediabench show that the efficient Cache achieves almost the same miss rate as a conventional two-way set associative Cache on average and with total memory-access energy savings of 30% compared with a conventional two-way set associative Cache.
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CODES+ISSS - An efficient direct mapped instruction Cache for application-specific embedded systems
Proceedings of the 3rd IEEE ACM IFIP international conference on Hardware software codesign and system synthesis - CODES+ISSS '05, 2005Co-Authors: Chuanjun ZhangAbstract:Caches may consume half of a microprocessor's total power and Cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing Cache power consumption and reducing Cache misses are important to reduce total energy consumption of embedded systems. Direct mapped Caches consume much less power than that of same sized set associative Caches but with a poor hit rate on average. Through experiments, we observe that memory space of direct mapped instruction Caches is not used efficiently in most embedded applications. We design an efficient Cache - a configurable instruction Cache that can be tuned to utilize the Cache sets efficiently for a particular application such that Cache memory is exploited more efficiently by index remapping. Experiments on 11 benchmarks drawn from Mediabench show that the efficient Cache achieves almost the same miss rate as a conventional two-way set associative Cache on average and with total memory-access energy savings of 30% compared with a conventional two-way set associative Cache.
S. Gurunarayanan - One of the best experts on this subject based on the ideXlab platform.
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Predictive Placement Scheme In Set-Associative Cache For Energy Efficient Embedded Systems
2008 International Conference on Signal Processing Communications and Networking, 2008Co-Authors: Biju K. Raveendran, Tsb Sudarshan, Avinash Patil, K. Randive, S. GurunarayananAbstract:This paper proposes a predictive placement scheme for Set-Associative Cache with better way-prediction hit, energy efficiency and performance. In this work, we consider the data Cache subsystem, as it is one of the most power consuming micro-architectural parts of an embedded system. We propose an energy efficient way-prediction scheme with predictive placement to improve prediction hit using minimal prediction bits. We show that, this scheme has an average energy saving 67.75% as compared to conventional caching scheme. Experimental results are obtained using Simplescalar 2.0 Cache simulator for SPEC95 benchmarks.
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Selective placement data Cache for low energy embedded system
Proceedings - 2006 14th International Conference on Advanced Computing and Communications ADCOM 2006, 2006Co-Authors: Biju K. Raveendran, Tangali S. Sudarshan, S. GurunarayananAbstract:This paper proposes a process aware selective placement scheme for N-way set associative Cache with the help of a victim set. In this work, we consider the data Cache subsystem, as it is one of the most power consuming microarchitectural parts of an embedded system and set associative Cache, being one of the popular mapping schemes for data Cache. We propose a selective placement scheme to reduce tag comparison and power consumption using victim set. We show that, this scheme has reduced the tag comparison by 70% and power saving by 72% as compared to conventional caching scheme. Experimental results are obtained using Simplescalar 2.0 Cache simulator for SPEC95benchmark suite.
Michael D Powell - One of the best experts on this subject based on the ideXlab platform.
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reducing set associative Cache energy via way prediction and selective direct mapping
International Symposium on Microarchitecture, 2001Co-Authors: Michael D Powell, Amit Agarwal, T N Vijaykumar, Babak Falsafi, Kaushik RoyAbstract:Set-Associative Caches achieve low miss rates for typical applications but result in significant energy dissipation. Set-Associative Caches minimize access time by probing all the data ways in parallel with the tag lookup, although the output of only the matching way is used. The energy spent accessing the other ways is wasted Eliminating the wasted energy by performing the data lookup sequentially following the tag lookup substantially increases Cache access time, and is unacceptable for high-performance L1 Caches. In this paper, we apply two previously-proposed techniques, way-prediction and selective direct-mapping, to reducing L1 Cache dynamic energy while maintaining high performance. The techniques predict the matching way and probe only the predicted way and not all the ways, achieving energy savings. While these techniques were originally proposed to improve Set-Associative Cache access times, this is the first paper to apply them to reducing Cache energy. We evaluate the effectiveness of these techniques in reducing L1 d-Cache, L1 i-Cache, and overall processor energy. Using these techniques, our Caches achieve the energy-delay of sequential access while maintaining the performance of parallel access. Relative to parallel access L1 i- and d-Caches, the techniques achieve overall processor energy-delay reduction of 8%, while perfect way-prediction with no performance degradation achieves 10% reduction. The performance degradation of the techniques is less than 3%, compared to an aggressive,.1-cycle, 4-way, parallel access Cache.
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MICRO - Reducing Set-Associative Cache energy via way-prediction and selective direct-mapping
Proceedings. 34th ACM IEEE International Symposium on Microarchitecture. MICRO-34, 1Co-Authors: Michael D Powell, Amit Agarwal, T N Vijaykumar, Babak Falsafi, Kaushik RoyAbstract:Set-Associative Caches achieve low miss rates for typical applications but result in significant energy dissipation. Set-Associative Caches minimize access time by probing all the data ways in parallel with the tag lookup, although the output of only the matching way is used. The energy spent accessing the other ways is wasted Eliminating the wasted energy by performing the data lookup sequentially following the tag lookup substantially increases Cache access time, and is unacceptable for high-performance L1 Caches. In this paper, we apply two previously-proposed techniques, way-prediction and selective direct-mapping, to reducing L1 Cache dynamic energy while maintaining high performance. The techniques predict the matching way and probe only the predicted way and not all the ways, achieving energy savings. While these techniques were originally proposed to improve Set-Associative Cache access times, this is the first paper to apply them to reducing Cache energy. We evaluate the effectiveness of these techniques in reducing L1 d-Cache, L1 i-Cache, and overall processor energy. Using these techniques, our Caches achieve the energy-delay of sequential access while maintaining the performance of parallel access. Relative to parallel access L1 i- and d-Caches, the techniques achieve overall processor energy-delay reduction of 8%, while perfect way-prediction with no performance degradation achieves 10% reduction. The performance degradation of the techniques is less than 3%, compared to an aggressive,.1-cycle, 4-way, parallel access Cache.