The Experts below are selected from a list of 2280 Experts worldwide ranked by ideXlab platform
Moinuddin K Qureshi - One of the best experts on this subject based on the ideXlab platform.
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accord enabling Associativity for gigascale dram caches by coordinating way install and way prediction
International Symposium on Computer Architecture, 2018Co-Authors: Vinson Young, Chiachen Chou, Aamer Jaleel, Moinuddin K QureshiAbstract:Stacked-DRAM technology has enabled high bandwidth gigascale DRAM caches. Since DRAM caches require a tag store of several tens of megabytes, commercial DRAM cache designs typically co-locate tag and data within the DRAM array. DRAM caches are organized as a direct-mapped structure so that the tag and data can be streamed out in a single access. While direct-mapped DRAM caches provide low hit-latency, they suffer from low hit-rate due to conflict misses. Ideally, we want the hit-rate of a Set-associative DRAM cache, without incurring additional latency and bandwidth costs of increasing Associativity. To address this problem, way prediction can be applied to a Set-associative DRAM cache to achieve the latency and bandwidth of a direct-mapped DRAM cache. Unfortunately, conventional way prediction policies typically require per-Set storage, causing multi-megabyte storage overheads for gigascale DRAM caches. If we can obtain accurate way prediction without incurring significant storage overheads, we can efficiently enable Set-Associativity for DRAM caches. This paper proposes Associativity via Coordinated Way-Install and Way-Prediction (ACCORD), a design that steers an incoming line to a "preferred way" based on the line address and uses the preferred way as the default way prediction. We propose two way-steering policies that are effective for 2-way caches. First, Probabilistic Way-Steering (PWS), which steers lines to a preferred way with high probability, while still allowing lines to be installed in an alternate way in case of conflicts. Second, Ganged Way-Steering (GWS), which steers lines of a spatially contiguous region to the way where an earlier line from that region was installed. On a 2-way cache, ACCORD (PWS+GWS) obtains a way prediction accuracy of 90% and retains a hit-rate similar to a baseline 2-way cache while incurring 320 bytes of storage overhead. We extend ACCORD to support highly-associative caches using a Skewed Way-Steering (SWS) design that steers a line to at-most two ways in the highly-associative cache. This design retains the low-latency of the 2-way ACCORD while obtaining most of the hit-rate benefits of a highly associative design. Our studies with a 4GB DRAM cache backed by non-volatile memory shows that ACCORD provides an average of 11% speedup (up to 54%) across a wide range of workloads.
Vinson Young - One of the best experts on this subject based on the ideXlab platform.
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accord enabling Associativity for gigascale dram caches by coordinating way install and way prediction
International Symposium on Computer Architecture, 2018Co-Authors: Vinson Young, Chiachen Chou, Aamer Jaleel, Moinuddin K QureshiAbstract:Stacked-DRAM technology has enabled high bandwidth gigascale DRAM caches. Since DRAM caches require a tag store of several tens of megabytes, commercial DRAM cache designs typically co-locate tag and data within the DRAM array. DRAM caches are organized as a direct-mapped structure so that the tag and data can be streamed out in a single access. While direct-mapped DRAM caches provide low hit-latency, they suffer from low hit-rate due to conflict misses. Ideally, we want the hit-rate of a Set-associative DRAM cache, without incurring additional latency and bandwidth costs of increasing Associativity. To address this problem, way prediction can be applied to a Set-associative DRAM cache to achieve the latency and bandwidth of a direct-mapped DRAM cache. Unfortunately, conventional way prediction policies typically require per-Set storage, causing multi-megabyte storage overheads for gigascale DRAM caches. If we can obtain accurate way prediction without incurring significant storage overheads, we can efficiently enable Set-Associativity for DRAM caches. This paper proposes Associativity via Coordinated Way-Install and Way-Prediction (ACCORD), a design that steers an incoming line to a "preferred way" based on the line address and uses the preferred way as the default way prediction. We propose two way-steering policies that are effective for 2-way caches. First, Probabilistic Way-Steering (PWS), which steers lines to a preferred way with high probability, while still allowing lines to be installed in an alternate way in case of conflicts. Second, Ganged Way-Steering (GWS), which steers lines of a spatially contiguous region to the way where an earlier line from that region was installed. On a 2-way cache, ACCORD (PWS+GWS) obtains a way prediction accuracy of 90% and retains a hit-rate similar to a baseline 2-way cache while incurring 320 bytes of storage overhead. We extend ACCORD to support highly-associative caches using a Skewed Way-Steering (SWS) design that steers a line to at-most two ways in the highly-associative cache. This design retains the low-latency of the 2-way ACCORD while obtaining most of the hit-rate benefits of a highly associative design. Our studies with a 4GB DRAM cache backed by non-volatile memory shows that ACCORD provides an average of 11% speedup (up to 54%) across a wide range of workloads.
P. Sadayappan - One of the best experts on this subject based on the ideXlab platform.
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Effective padding of multidimensional arrays to avoid cache conflict misses
ACM SIGPLAN Notices, 2016Co-Authors: Changwan Hong, Wenlei Bao, Albert Cohen, Sriram Krishnamoorthy, Louis-noël Pouchet, Fabrice Rastello, J. Ramanujam, P. SadayappanAbstract:Caches are used to significantly improve performance. Even with high degrees of Set Associativity, the number of accessed data elements mapping to the same Set in a cache can easily exceed the degree of Associativity. This can cause conflict misses and lower performance, even if the working Set is much smaller than cache capacity. Array padding (increasing the size of array dimensions) is a well-known optimization technique that can reduce conflict misses. In this paper, we develop the first algorithms for optimal padding of arrays aimed at a Set-associative cache for arbitrary tile sizes. In addition, we develop the first solution to padding for nested tiles and multi-level caches. Experimental results with multiple benchmarks demonstrate a significant performance improvement from padding.
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Effective padding of multidimensional arrays to avoid cache conflict misses
HAL CCSD, 2016Co-Authors: Hong Changwan, Bao Wenlei, Cohen Albert, Krishnamoorthy Sriram, Pouchet Louis-noël, Rastello Fabrice, Ramanujam J., P. SadayappanAbstract:International audienceCaches are used to significantly improve performance. Even with highdegrees of Set Associativity, the number of accessed data elements mappingto the same Set in a cache can easily exceed the degree of Associativity. This can causeconflict misses and lower performance, even if the working Setis much smaller than cache capacity. Array padding (increasing the size of array dimensions) is a well-known optimization technique that can reduce conflict misses.In this paper, we develop the first algorithms for optimal padding ofarrays aimed at a Set-associative cache for arbitrary tile sizes. Inaddition, wedevelop the first solution to padding for nested tiles andmulti-level caches.Experimental results with multiple benchmarksdemonstrate a significant performance improvement from padding
Aamer Jaleel - One of the best experts on this subject based on the ideXlab platform.
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accord enabling Associativity for gigascale dram caches by coordinating way install and way prediction
International Symposium on Computer Architecture, 2018Co-Authors: Vinson Young, Chiachen Chou, Aamer Jaleel, Moinuddin K QureshiAbstract:Stacked-DRAM technology has enabled high bandwidth gigascale DRAM caches. Since DRAM caches require a tag store of several tens of megabytes, commercial DRAM cache designs typically co-locate tag and data within the DRAM array. DRAM caches are organized as a direct-mapped structure so that the tag and data can be streamed out in a single access. While direct-mapped DRAM caches provide low hit-latency, they suffer from low hit-rate due to conflict misses. Ideally, we want the hit-rate of a Set-associative DRAM cache, without incurring additional latency and bandwidth costs of increasing Associativity. To address this problem, way prediction can be applied to a Set-associative DRAM cache to achieve the latency and bandwidth of a direct-mapped DRAM cache. Unfortunately, conventional way prediction policies typically require per-Set storage, causing multi-megabyte storage overheads for gigascale DRAM caches. If we can obtain accurate way prediction without incurring significant storage overheads, we can efficiently enable Set-Associativity for DRAM caches. This paper proposes Associativity via Coordinated Way-Install and Way-Prediction (ACCORD), a design that steers an incoming line to a "preferred way" based on the line address and uses the preferred way as the default way prediction. We propose two way-steering policies that are effective for 2-way caches. First, Probabilistic Way-Steering (PWS), which steers lines to a preferred way with high probability, while still allowing lines to be installed in an alternate way in case of conflicts. Second, Ganged Way-Steering (GWS), which steers lines of a spatially contiguous region to the way where an earlier line from that region was installed. On a 2-way cache, ACCORD (PWS+GWS) obtains a way prediction accuracy of 90% and retains a hit-rate similar to a baseline 2-way cache while incurring 320 bytes of storage overhead. We extend ACCORD to support highly-associative caches using a Skewed Way-Steering (SWS) design that steers a line to at-most two ways in the highly-associative cache. This design retains the low-latency of the 2-way ACCORD while obtaining most of the hit-rate benefits of a highly associative design. Our studies with a 4GB DRAM cache backed by non-volatile memory shows that ACCORD provides an average of 11% speedup (up to 54%) across a wide range of workloads.
Chiachen Chou - One of the best experts on this subject based on the ideXlab platform.
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accord enabling Associativity for gigascale dram caches by coordinating way install and way prediction
International Symposium on Computer Architecture, 2018Co-Authors: Vinson Young, Chiachen Chou, Aamer Jaleel, Moinuddin K QureshiAbstract:Stacked-DRAM technology has enabled high bandwidth gigascale DRAM caches. Since DRAM caches require a tag store of several tens of megabytes, commercial DRAM cache designs typically co-locate tag and data within the DRAM array. DRAM caches are organized as a direct-mapped structure so that the tag and data can be streamed out in a single access. While direct-mapped DRAM caches provide low hit-latency, they suffer from low hit-rate due to conflict misses. Ideally, we want the hit-rate of a Set-associative DRAM cache, without incurring additional latency and bandwidth costs of increasing Associativity. To address this problem, way prediction can be applied to a Set-associative DRAM cache to achieve the latency and bandwidth of a direct-mapped DRAM cache. Unfortunately, conventional way prediction policies typically require per-Set storage, causing multi-megabyte storage overheads for gigascale DRAM caches. If we can obtain accurate way prediction without incurring significant storage overheads, we can efficiently enable Set-Associativity for DRAM caches. This paper proposes Associativity via Coordinated Way-Install and Way-Prediction (ACCORD), a design that steers an incoming line to a "preferred way" based on the line address and uses the preferred way as the default way prediction. We propose two way-steering policies that are effective for 2-way caches. First, Probabilistic Way-Steering (PWS), which steers lines to a preferred way with high probability, while still allowing lines to be installed in an alternate way in case of conflicts. Second, Ganged Way-Steering (GWS), which steers lines of a spatially contiguous region to the way where an earlier line from that region was installed. On a 2-way cache, ACCORD (PWS+GWS) obtains a way prediction accuracy of 90% and retains a hit-rate similar to a baseline 2-way cache while incurring 320 bytes of storage overhead. We extend ACCORD to support highly-associative caches using a Skewed Way-Steering (SWS) design that steers a line to at-most two ways in the highly-associative cache. This design retains the low-latency of the 2-way ACCORD while obtaining most of the hit-rate benefits of a highly associative design. Our studies with a 4GB DRAM cache backed by non-volatile memory shows that ACCORD provides an average of 11% speedup (up to 54%) across a wide range of workloads.