The Experts below are selected from a list of 141 Experts worldwide ranked by ideXlab platform
Sanjeev Kumar - One of the best experts on this subject based on the ideXlab platform.
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ICN (1) - Effect of unbalanced bursty traffic on Memory-sharing schemes for internet Switching architecture
Networking - ICN 2005, 2005Co-Authors: Alvaro Munoz, Sanjeev KumarAbstract:Shared-Memory based packet Switches are increasingly being used for high-performance Internet Switches and routers. The Shared-Memory Switches are known to provide better throughput and packet-loss performance for bursty data traffic in high-speed networks and Internets compared with other buffering strategies under conditions of identical Memory resource deployed in the Shared-Memory Switch. The scheme to share the common Memory resource among various broadband lines has direct impact on the throughput and packet-loss performance of the Switch. In this paper, we compare the effect of unbalanced bursty traffic on commonly used Memory-sharing schemes, namely the individual-static threshold based, global-static threshold based, dynamic threshold based and SMDA based Memory-sharing schemes.
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The sliding-window packet Switch: a new class of packet Switch architecture with plural Memory modules and decentralized control
IEEE Journal on Selected Areas in Communications, 2003Co-Authors: Sanjeev KumarAbstract:Shared-Memory based packet Switches are known to provide the best possible throughput performance for bursty data traffic in high-speed packet networks and internets compared with other buffering strategies under conditions of identical Memory resources deployed in the Switch. However, scaling of Shared-Memory packet Switches to a larger size has been restricted mainly due to the physical limitations imposed by the Memory-access speed and the centralized control for Switching functions in Shared-Memory Switches. A new scalable architecture for a Shared-Memory packet Switch, called the sliding-window (SW) Switch, is proposed to overcome these limitations. The SW Switch introduces a new class of Switching architecture, where physically separate multiple Memory modules are logically Shared among all the ports of the Switch, and the control is decentralized. The SW Switch alleviates the bottleneck caused by the centralized control of Switching functions in large Shared-Memory Switches. Decentralized Switching functions enable the SW Switch to operate in a pipeline fashion to enhance scalability and Switching capacity compared with that of previously known classes of Shared-Memory Switch architecture.
Neeraj K. Sharma - One of the best experts on this subject based on the ideXlab platform.
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Performance of a large multicast ATM Switch
Telecommunication Systems, 2000Co-Authors: Neeraj K. SharmaAbstract:In this paper, we present the design of a large self-routing multicast ATM Switch. The Switch consists of a sorting network followed by a 3-stage routing network. We first present a simple design of a large sorting network built using small sized Shared Memory that can be used as a building block for a large sorting network. Small sized Shared Memory is also used in the 3-stage routing network making the Switch modular and easy to implement using current VLSI technology. As the network uses Shared Memory modules, multicasting functionality is easily built into the network. The performance of the proposed network is compared with an equivalent completely Shared Memory Switch using computer simulations under bursty traffic model. The results show that the proposed network has better performance in terms of cell loss ratio than the completely Shared Memory Switch under moderate to heavy traffic load (0.6 ≤ effective offered load ≤ 1.2). Furthermore, multicast cell delays are drastically improved.
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Modular design of a large multicast ATM Switch
IEEE GLOBECOM 1998 (Cat. NO. 98CH36250), 1Co-Authors: Neeraj K. SharmaAbstract:In this paper, we present the design of a large self routing multicast ATM Switch. The Switch consists of a sorting network followed by a 3-stage routing network. We first present a simple design of a large sorting network, built using a small sized Shared Memory that can be used as a building block for a large sorting network. The small sized Shared Memory is also used in the 3-stage routing network making the Switch modular and easy to implement using current VLSI technology. As the network uses Shared Memory modules, multicasting functionality is easily built into the network. The performance of the proposed network is compared with an equivalent completely Shared Memory Switch using computer simulations under bursty traffic model. The results show that the proposed network has better performance in terms of cell loss rate than the completely Shared Memory Switch under moderate to heavy traffic load (0.6/spl les/effective offered load/spl les/1.2). Furthermore, multicast cell delays are drastically improved.
Y U Shaohua - One of the best experts on this subject based on the ideXlab platform.
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a dual threshold buffer management scheme in Shared Memory Switch fabric
Acta Electronica Sinica, 2009Co-Authors: Y U ShaohuaAbstract:This paper concerns with the threshold control problem in a Shared Memory Switch fabric.Traditional threshold control schemes are insensitive to the runtime traffic scenarios,and lack an efficient support for multicast forwarding.A novel scheme is presented in this paper,which aims to balance traffic pressure to the output ports and keep the system in an equilibrium state.Derived from a further exploitation of the developed effective bandwidth theory,the proposed scheme delineates an expressive formula that can calculate the shift of bandwidth burden to Memory allocation.The association between bandwidth and Memory utilization can be used to balance the traffic pressure by adjusting the per-queue thresholds in the Shared Memory.Furthermore,the presented framework can also encompass the support for multicast cells.The result of simulation shows that the scheme outperforms the traditional dynamic threshold in terms of efficiency and fairness under variant traffic modes.
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a traffic equilibrium base queue threshold scheme in Shared Memory Switch
Geomatics and Information Science of Wuhan University, 2008Co-Authors: Y U ShaohuaAbstract:This paper investigates the queue threshold control scheme in Shared Memory Switches.Traditional queue control scheme employs a global threshold,which is derived from current queue length and lacks of the consideration of traffic scenarios.The presented work uses the traffic pressure as a main criterion to establish a per-queue threshold.In this sense,every output port bears the same traffic pressure.The scheme keeps the balance of the common Memory in the sense of average,and relieves the demand of buffer space in times of bursty traffic.The result of simulation shows that the proposed scheme outperforms the traditional dynamic threshold in terms of efficiency.
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an effective traffic based dual threshold queue control scheme in Shared Memory Switch
International Conference on Wireless Communications Networking and Mobile Computing, 2007Co-Authors: Wang Yang, Zhan Yichun, Y U ShaohuaAbstract:This paper investigates the queue control or buffer management problem in Shared Memory Switches. Traditional methods such as dynamic threshold and the newly proposed such as decay function threshold take decision largely based on the current total queue length. The dual threshold method proposed by this paper considers the traffic scenario as the main factor to decide a per-port threshold. Each port maintains a common traffic intensity, which is accounted for by the traffic rate and the allotted buffer. The traffic intensity takes shape from the classical effective bandwidth theory, yet the formula devised by the theory is too complex to implement. This paper reduces the formula to a simple form that is eligible in the runtime environment with little loss of accuracy. Keeping the common traffic intensity by dynamically adjust the per-port threshold can maintain the system equilibrium and reach a global optimality. Simulation shows the proposed scheme outperforms the tradition dynamic thresholds significantly.
Alexander Sirotkin - One of the best experts on this subject based on the ideXlab platform.
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Admission control in Shared Memory Switches
Journal of Scheduling, 2018Co-Authors: Patrick Eugster, Sergey Nikolenko, Alex Kesselman, Kirill Kogan, Alexander SirotkinAbstract:Cloud applications bring new challenges to the design of network elements, in particular the burstiness of traffic workloads. A Shared Memory Switch is a good candidate architecture to exploit buffer capacity; in this work, we analyze the performance of this architecture. Our goal is to explore the impact of additional traffic characteristics such as varying processing requirements and packet values on objective functions. The outcome of this work is a better understanding of the relevant parameters for buffer management to achieve better performance in dynamic environments of data centers. We consider a model that captures more of the properties of the target architecture than previous work and consider several scheduling and buffer management algorithms that are specifically designed to optimize its performance. In particular, we provide analytic guarantees for the throughput performance of our algorithms that are independent from specific distributions of packet arrivals. We furthermore report on a comprehensive simulation study which validates our analytic results.
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Heterogeneous packet processing in Shared Memory buffers
Journal of Parallel and Distributed Computing, 2017Co-Authors: Patrick Eugster, Kirill Kogan, Sergey I Nikolenko, Alexander SirotkinAbstract:Abstract Packet processing increasingly involves heterogeneous requirements. We consider the well-known model of a Shared Memory Switch with bounded-size buffer and generalize it in two directions. First, we consider unit-sized packets labeled with an output port and a processing requirement (i.e., packets with heterogeneous processing), maximizing the number of transmitted packets. We analyze the performance of buffer management policies under various characteristics via competitive analysis that provides uniform guarantees across traffic patterns (Borodin and ElYaniv 1998). We propose the Longest-Work-Drop policy and show that it is at most 2 -competitive and at least 2 -competitive. Second, we consider another generalization, posed as an open problem in Goldwasser (2010), where each unit-sized packet is labeled with an output port and intrinsic value, and the goal is to maximize the total value of transmitted packets. We show first results in this direction and define a scheduling policy that, as we conjecture, may achieve constant competitive ratio. We also present a comprehensive simulation study that validates our results.
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SIROCCO - Essential Traffic Parameters for Shared Memory Switch Performance
Structural Information and Communication Complexity, 2015Co-Authors: Patrick Eugster, Alex Kesselman, Kirill Kogan, Sergey I Nikolenko, Alexander SirotkinAbstract:Cloud applications bring new challenges to the design of network elements, in particular accommodating for the burstiness of traffic workloads. Shared Memory Switches represent the best candidate architecture to exploit buffer capacity; we analyze the performance of this architecture. Our goal is to explore the impact of additional traffic characteristics such as varying processing requirements and packet values on objective functions. The outcome of this work is a better understanding of the relevant parameters for buffer management to achieve better performance in dynamic environments of data centers. We consider a model that captures more of the properties of the target architecture than previous work and consider several scheduling and buffer management algorithms that are specifically designed to optimize its performance. In particular, we provide analytic guarantees for the throughput performance of our algorithms that are independent from specific distributions of packet arrivals. We furthermore report on a comprehensive simulation study which validates our analytic results.
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essential traffic parameters for Shared Memory Switch performance
SIROCCO 2015 Post-Proceedings of the 22nd International Colloquium on Structural Information and Communication Complexity - Volume 9439, 2015Co-Authors: Patrick Eugster, Alex Kesselman, Kirill Kogan, Sergey I Nikolenko, Alexander SirotkinAbstract:Cloud applications bring new challenges to the design of network elements, in particular accommodating for the burstiness of traffic workloads. Shared Memory Switches represent the best candidate architecture to exploit buffer capacity; we analyze the performance of this architecture. Our goal is to explore the impact of additional traffic characteristics such as varying processing requirements and packet values on objective functions. The outcome of this work is a better understanding of the relevant parameters for buffer management to achieve better performance in dynamic environments of data centers. We consider a model that captures more of the properties of the target architecture than previous work and consider several scheduling and buffer management algorithms that are specifically designed to optimize its performance. In particular, we provide analytic guarantees for the throughput performance of our algorithms that are independent from specific distributions of packet arrivals. We furthermore report on a comprehensive simulation study which validates our analytic results.
Ashwin Gumaste - One of the best experts on this subject based on the ideXlab platform.
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design of a Shared Memory carrier ethernet Switch compliant to provider backbone bridging traffic engineering ieee802 1qay
High Performance Switching and Routing, 2012Co-Authors: Saurabh Mehta, Ashutosh Upadhyaya, Sarvesh Bidkar, Ashwin GumasteAbstract:Carrier Ethernet is emerging as a new transport paradigm across metropolitan and core networks. Provider Backbone Bridging-Traffic Engineering or PBB-TE was standardized in the IEEE as 802.1Qay as a mechanism to provide a dedicated transport service at the Ethernet layer. This paper discusses implementation of the PBB-TE standard using Shared Memory Switch architecture, though the same architecture argument can be extended to implement MPLS-TP (the other manifestation of Carrier Ethernet). While Shared Memory Switch architectures have been well investigated, we provide to the best of our knowledge the first carrier-class aggregation Switch implemented in a single Field Programmable Gate Array (FPGA). This low-cost implementation paves the way for advances in Carrier Ethernet technologies to be made available to the access part of the network using rapid prototyping and commercial off the shelf components. The Switch architecture supports multiple QoS levels and implements circuit emulation to transport traditional circuit services over a packet backbone. A rigorous simulation study validates our effort.
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HPSR - Design of a Shared Memory Carrier Ethernet Switch compliant to Provider Backbone Bridging-Traffic Engineering (IEEE802.1Qay)
2012 IEEE 13th International Conference on High Performance Switching and Routing, 2012Co-Authors: Saurabh Mehta, Ashutosh Upadhyaya, Sarvesh Bidkar, Ashwin GumasteAbstract:Carrier Ethernet is emerging as a new transport paradigm across metropolitan and core networks. Provider Backbone Bridging-Traffic Engineering or PBB-TE was standardized in the IEEE as 802.1Qay as a mechanism to provide a dedicated transport service at the Ethernet layer. This paper discusses implementation of the PBB-TE standard using Shared Memory Switch architecture, though the same architecture argument can be extended to implement MPLS-TP (the other manifestation of Carrier Ethernet). While Shared Memory Switch architectures have been well investigated, we provide to the best of our knowledge the first carrier-class aggregation Switch implemented in a single Field Programmable Gate Array (FPGA). This low-cost implementation paves the way for advances in Carrier Ethernet technologies to be made available to the access part of the network using rapid prototyping and commercial off the shelf components. The Switch architecture supports multiple QoS levels and implements circuit emulation to transport traditional circuit services over a packet backbone. A rigorous simulation study validates our effort.