The Experts below are selected from a list of 33960 Experts worldwide ranked by ideXlab platform
Dae-yong Jeong - One of the best experts on this subject based on the ideXlab platform.
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Reaction and interfacial structures between Ag paste with tellurite glass frits and Si Wafer for solar cells
Metals and Materials International, 2015Co-Authors: Seunggon Choi, Sunghwan Cho, Jungki Lee, Dae-yong Jeong, Hyungsun KimAbstract:Tellurite glass frits with different SiO2/PbO ratios were produced and characterized for use in the Ag paste in the electrodes of polycrystalline Si solar cells. The thermophySical properties of the frits were determined uSing differential scanning calorimetry, and their fuSion behaviors were studied uSing hot-stage microscopy. Glass frits in the Ag pastes reacted with the Si Wafer. The interfacial structure between the Ag electrodes and the Si Wafer was observed uSing scanning electrode microscopy. Depending on their compoSitions, the glass frits in the Ag paste exhibited different contact behaviors with the Si Wafer substrate. This led to different interfacial structures between Ag electrodes and the Si Wafer. The morphology of the interfacial structure Significantly affected the electrical properties of the resulting Si solar cells. The viscoSity of the fused glass frits at temperatures above their flow-point temperature affected the degree of Si Wafer etching and the distribution of recrystallites on the n+ emitter.
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stress controlled pb zr0 52ti0 48 o3 thick films by thermal expanSion mismatch between substrate and pb zr0 52ti0 48 o3 film
Journal of Applied Physics, 2011Co-Authors: Woon Ha Yoon, Jong Jin Choi, Byung Dong Hahn, Dong Soo Park, Shashank Priya, Dae-yong JeongAbstract:Polycrystalline Pb(Zr0.52Ti0.48)O3 (PZT) thick films (thickness ∼10 μm) were successfully fabricated by uSing a novel aerosol depoSition technique on Si Wafer, sapphire, and Single crystal yitria stabilized zirconia (YSZ) Wafer substrates with Pt electrodes and their dielectric, ferroelectric, and piezoelectric properties, and in-plane stresses were investigated. The films with different stress conditions were Simply controlled by the coefficient of thermal expanSion (CTE) misfit of PZT films and substrates. The results showed that the films bearing in-plane compresSive stress depoSited on the YSZ and sapphire substrates have superior dielectric, ferroelectric (∼90%), and piezoelectric (>200%) properties over that of the Si Wafer. Among these three substrates, YSZ shows superior properties of the PZT films. However, films on Si Wafer with tenSile stress present lower properties. We believed that in-plane compresSive stresses within the films are benefited, the formation of c-domain parallel to the thickne...
Woon Ha Yoon - One of the best experts on this subject based on the ideXlab platform.
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stress controlled pb zr0 52ti0 48 o3 thick films by thermal expanSion mismatch between substrate and pb zr0 52ti0 48 o3 film
Journal of Applied Physics, 2011Co-Authors: Woon Ha Yoon, Jong Jin Choi, Byung Dong Hahn, Dong Soo Park, Shashank Priya, Dae-yong JeongAbstract:Polycrystalline Pb(Zr0.52Ti0.48)O3 (PZT) thick films (thickness ∼10 μm) were successfully fabricated by uSing a novel aerosol depoSition technique on Si Wafer, sapphire, and Single crystal yitria stabilized zirconia (YSZ) Wafer substrates with Pt electrodes and their dielectric, ferroelectric, and piezoelectric properties, and in-plane stresses were investigated. The films with different stress conditions were Simply controlled by the coefficient of thermal expanSion (CTE) misfit of PZT films and substrates. The results showed that the films bearing in-plane compresSive stress depoSited on the YSZ and sapphire substrates have superior dielectric, ferroelectric (∼90%), and piezoelectric (>200%) properties over that of the Si Wafer. Among these three substrates, YSZ shows superior properties of the PZT films. However, films on Si Wafer with tenSile stress present lower properties. We believed that in-plane compresSive stresses within the films are benefited, the formation of c-domain parallel to the thickne...
Sarah Eunkyung Kim - One of the best experts on this subject based on the ideXlab platform.
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Stress analySis of stacked Si Wafer in 3D WLP
Current Applied Physics, 2011Co-Authors: Ki-ho Maeng, Sung-geun Kang, Youngrae Kim, Sungdong Kim, Sarah Eunkyung KimAbstract:Abstract In 3D Wafer-stacking technology, one of the major manufacturing issues is Wafer warpage because it causes process and product failures, such as delamination, cracking, mechanical stresses, and even electrical failure. In this study, the Wafer warpage and local strain of thinned Si Wafers in a Wafer stack were investigated. A blanket Cu film was depoSited on a Si Wafer by a sputtering process. Two Cu depoSited Wafers were bonded by a thermo-compresSion method, and a stacked Wafer was thinned down to 30 μm. The three Wafers were then stacked on a Si Wafer substrate. The Wafer warpage and local strain of each stacked Si Wafer were measured by film-stress measurement and the convergent-beam electron diffraction technique of transmisSion electron microscopy, respectively. An emphaSis was placed on the effects of Wafer stacking by Cu bonding and Si thinning on stress development in a thinned Si Wafer. As the number of Wafers in a stack increased, Wafer warpage became severe, and the local strain in thinned Si Wafers near the Si/Cu interface was increased.
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study of thinned Si Wafer warpage in 3d stacked Wafers
Microelectronics Reliability, 2010Co-Authors: Youngrae Kim, Sungkeun Kang, Sarah Eunkyung KimAbstract:Abstract 3D (three-dimenSional) Wafer stacking technology has been developed extenSively recently. One of the many technical challenges in 3D stacked Wafers, and one of the most important, is Wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within Wafer (WIW) uniformity and even electrical failure. In this study, the Wafer warpage of thinned Si Wafers in stacked Wafers has been evaluated. Si Wafer or glass was used as a thick substrate, and Cu or polyimide was used as the bonding material. The top Si Wafer in the bonded stack was ground down to 20–100 μm, and Wafer curvature was measured. Wafer curvature and how it relates to bonding material, substrate material of the stacked layers, and thickness of thinned Si Wafer will be discussed.
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Microelectronics Reliability - Study of thinned Si Wafer warpage in 3D stacked Wafers
Microelectronics Reliability, 2010Co-Authors: Youngrae Kim, Sungkeun Kang, Sarah Eunkyung KimAbstract:Abstract 3D (three-dimenSional) Wafer stacking technology has been developed extenSively recently. One of the many technical challenges in 3D stacked Wafers, and one of the most important, is Wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within Wafer (WIW) uniformity and even electrical failure. In this study, the Wafer warpage of thinned Si Wafers in stacked Wafers has been evaluated. Si Wafer or glass was used as a thick substrate, and Cu or polyimide was used as the bonding material. The top Si Wafer in the bonded stack was ground down to 20–100 μm, and Wafer curvature was measured. Wafer curvature and how it relates to bonding material, substrate material of the stacked layers, and thickness of thinned Si Wafer will be discussed.
Shinichi Takagi - One of the best experts on this subject based on the ideXlab platform.
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ingaasp photonic wire based ultrasmall arrayed waveguide grating multiplexer on Si Wafer
Applied Physics Express, 2009Co-Authors: Mitsuru Takenaka, Masafumi Yokoyama, Masakazu Sugiyama, Yoshiaki Nakano, Shinichi TakagiAbstract:Extremely compact low-loss four channel arrayed waveguide grating (AWG) with a channel spacing of 600 GHz was demonstrated with InP-based photonic wire waveguides uSing III–V semiconductor on insulator (III–V-OI) on Si Wafer. The III–V-OI substrate was fabricated by direct Wafer bonding of an InGaAsP/InP Wafer to a thermally oxidized Si Wafer. The InGaAsP ultrahigh index contrast photonic wire waveguide allowed the Size reduction of the AWG down to 147×92 µm2. The measured insertion loss was approximately 6 dB and the crosstalk of around -10 dB was obtained. The transmisSion power nonuniformity of the four wavelength channel was less than 1 dB.
Isao Kusunoki - One of the best experts on this subject based on the ideXlab platform.
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Vacuum sealing uSing surface activation bonding of Si Wafer
Vacuum, 2009Co-Authors: Miki Inamura, Noriko Yoshida, Isao KusunokiAbstract:Bonding technology of Si Wafer for vacuum seal is important in MEMS. We have tried the vacuum seal uSing surface activation bonding without any binder. It is the ultimate bonding technique and gives the precise dimenSion due to the direct contact. The technique is, however, not easy. We have investigated the surface conditions in order to achieve the bonding. The surfaces cleaned by Ar ion beam bombardment were measured by XPS and AFM. The natural oxide on the Si surface was removed by Ar ion bombardment. The surface roughness depended on the condition and the irradiation time of the Ar ion beam. The surface bonding at room temperature was achieved for the clean surface of the surface roughness less than Ra = 1 nm, but it was not done with the rough surfaces more than Ra > 2 nm. The vacuum sealing was checked uSing the cavities made in the Si Wafer. The cavity part sealed in vacuum was depressed in the atmosphere, which was measured uSing a needle-contact profiler and a 3D laser profiler. The gas in the cavity was measured with a mass spectrometer by clashing the seal in vacuum. Any other gas except Ar gas closed in the cavity was not detected. We concluded that the vacuum sealing uSing surface activation bonding of Si Wafer was achieved. The sealing condition has not changed even after one year.
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Vacuum sealing uSing surface activation bonding of Si Wafer
Vacuum, 2009Co-Authors: Miki Inamura, Noriko Yoshida, Isao KusunokiAbstract:Bonding technology of Si Wafer for vacuum seal is important in MEMS. We have tried the vacuum seal uSing surface activation bonding without any binder. It is the ultimate bonding technique and gives the precise dimenSion due to the direct contact. The technique is, however, not easy. We have investigated the surface conditions in order to achieve the bonding. The surfaces cleaned by Ar ion beam bombardment were measured by XPS and AFM. The natural oxide on the Si surface was removed by Ar ion bombardment. The surface roughness depended on the condition and the irradiation time of the Ar ion beam. The surface bonding at room temperature was achieved for the clean surface of the surface roughness less than Ra = 1 nm, but it was not done with the rough surfaces more than Ra > 2 nm. The vacuum sealing was checked uSing the cavities made in the Si Wafer. The cavity part sealed in vacuum was depressed in the atmosphere, which was measured uSing a needle-contact profiler and a 3D laser profiler. The gas in the cavity was measured with a mass spectrometer by clashing the seal in vacuum. Any other gas except Ar gas closed in the cavity was not detected. We concluded that the vacuum sealing uSing surface activation bonding of Si Wafer was achieved. The sealing condition has not changed even after one year.