Signal Bandwidth

14,000,000 Leading Edge Experts on the ideXlab platform

Scan Science and Technology

Contact Leading Edge Experts & Companies

Scan Science and Technology

Contact Leading Edge Experts & Companies

The Experts below are selected from a list of 83889 Experts worldwide ranked by ideXlab platform

Connie J Changhasnain - One of the best experts on this subject based on the ideXlab platform.

K A Shore - One of the best experts on this subject based on the ideXlab platform.

E Sanchezsinencio - One of the best experts on this subject based on the ideXlab platform.

  • a continuous time sigma delta modulator with 88 db dynamic range and 1 1 mhz Signal Bandwidth
    IEEE Journal of Solid-state Circuits, 2004
    Co-Authors: Shouli Yan, E Sanchezsinencio
    Abstract:

    This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz Signal Bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.

  • a continuous time spl sigma spl delta modulator with 88db dynamic range and 1 1mhz Signal Bandwidth
    International Solid-State Circuits Conference, 2003
    Co-Authors: Shouli Yan, E Sanchezsinencio
    Abstract:

    A baseband continuous-time multi-bit /spl Sigma//spl Delta/ modulator achieves 88dB dynamic range over a 1.1MHz Signal Bandwidth consuming 62mW from a 3.3V supply. Excess loop delay encountered in conventional continuous-time modulators is eliminated by the proposed architecture. Clock-jitter sensitivity is considerably reduced compared with prior designs.

S F Lim - One of the best experts on this subject based on the ideXlab platform.

Yanhua Hong - One of the best experts on this subject based on the ideXlab platform.