The Experts below are selected from a list of 33057 Experts worldwide ranked by ideXlab platform
Peter Magill - One of the best experts on this subject based on the ideXlab platform.
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high spectral efficiency 114 gb s transmission using polmux rz 8psk modulation format and single ended digital coherent detection technique
Journal of Lightwave Technology, 2009Co-Authors: Xiang Zhou, Jianjun Yu, Dayou Qian, Ting Wang, Guodong Zhang, Peter MagillAbstract:Employing spectrally efficient PolMux-RZ-8PSK modulation format and single-ended digital coherent detection technique, we demonstrate 8 times 114-Gb/s DWDM transmission over 640 km of SSMF on a 25-GHz grid with record spectral efficiency of 4.2 bit/s/Hz, utilizing no optical dispersion compensation or Raman amplification. We show that the distortion caused by the direct square-law detection of the Signal Component with single-ended photo detection can be effectively mitigated by a novel DSP algorithm.
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high spectral efficiency 114 gb s transmission using polmux rz 8psk modulation format and single ended digital coherent detection technique
OFC NFOEC 2008, 2009Co-Authors: Xiang Zhou, Jianjun Yu, Dayou Qian, Ting Wang, Guodong Zhang, Peter MagillAbstract:-Employing spectrally efficient PolMux.RZ.8PSK modulation format and single-ended digital coherent detection technique, we demonstrate 8 x 114-Gb/s DWDM transmission over 640 km of SSMF on a 25-GHz grid with record spectral efficiency of 4.2 bit/s/Hz, utilizing no optical dispersion compensation or Raman amplification. We show that the distortion caused by the direct square-law detection of the Signal Component with single-ended photo detection can be effectively mitigated by a novel DSP algorithm.
Jui-yuan Yu - One of the best experts on this subject based on the ideXlab platform.
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A low power all-digital Signal Component separator for uneven multi-level LINC systems
2011 Proceedings of the ESSCIRC (ESSCIRC), 2011Co-Authors: Tsan-wen Chen, Ping-yuan Tsai, Dieter De Moitie, Jui-yuan YuAbstract:This paper presents an all-digital Signal Component separator (SCS) with low power overhead for uneven multilevel LINC (UMLINC) systems, including a multi-level phase calculator (MLPC) and a digitally-control phase shifter (DCPS) pair. The optimal gain level with branch mismatch consideration is proposed to achieve maximal average efficiency 44.82%. This SCS chip is manufactured in 90 nm standard CMOS process with an active area 0.5 mm2. The required phases of branch Signals and PA gain controls can be calculated by the proposed MLPC. Instead of four DACs, the DCPS pair with a continuous PVT monitor is also proposed to generate the phase-modulated Signals accurately at IF frequency 80 MHz with 8-bit resolution. By applying voltage scaling and source gating on DSP functions and DCPSs respectively, 81.32% power cost of SCS can be reduced, and the overall power is only 0.65 mW. With the proposed SCS, the EVM of -31.06 dB using 64-QAM OFDM Signals can be achieved for high-efficiency UMLINC systems.
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A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters
IEEE Journal of Solid-State Circuits, 2011Co-Authors: Tsan-wen Chen, Ping-yuan Tsai, Jui-yuan YuAbstract:Linear amplification with nonlinear Components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital Signal Component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06 mm2. The DCPS can generate phase-modulated Signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34°). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 μW which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15° phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10° phase mismatch, the system EVM of - 29.81 dB and ACPR of - 34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM Signals.
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A low-power all-digital Signal Component separator for OFDM LINC systems
The 2010 International Conference on Green Circuits and Systems, 2010Co-Authors: Tsan-wen Chen, Ping-yuan Tsai, Jui-yuan YuAbstract:LINC can achieve linear amplification by using high-efficiency amplifiers. This work presents an all-digital LINC Signal Component separator (SCS) including the phase calculation digital Signal processing and two digital-control phase shifters (DCPSs). With the duplicate DCPSs, a pre-calibration scheme is introduced to guarantee the codeword-to-phase linearity and accuracy under different PVT conditions. The proposed DCPS design provides 8-bit resolution at 100 MHz with RMS error 10 ps (0.36°) resulting in system EVM -29.21 dB with 64-QAM OFDM Signals, and the performance can meet the requirements specified in IEEE 802.11a. This work is implemented in a 90 nm CMOS process. With the voltage scaling scheme to specific power domains and the low-complexity DCPS design, the overall SCS consumes 850.51 μW from 0.5 V and 1.0 V supplies.
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A sub-mW all-digital Signal Component separator with branch mismatch compensation for OFDM LINC transmitters
2010 IEEE Asian Solid-State Circuits Conference, 2010Co-Authors: Tsan-wen Chen, Ping-yuan Tsai, Jui-yuan YuAbstract:This paper presents a sub-mW all-digital Signal Component separator (SCS) with a novel branch mismatch compensation scheme for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. This chip is manufactured in 90nm standard CMOS process with active area 0.06mm2. The DCPS can generate phase-modulated Signal at IF 100MHz with 8-bit resolution and RMS error 9.33ps (0.34°). The phase calculation can be operated with maximum 50MHz speed at 0.5V supply voltage, resulting in 73.88% power reduction, and the overall SCS power is only 949.5μW. With the aid of this SCS, the branch mismatch compensation scheme provides 0.02dB gain and 0.15° phase fine-tune resolution. The system EVM with 64-QAM OFDM Signals is -29.81dB, and the spectrum can pass the mask test of IEEE 802.11a.
Xiang Zhou - One of the best experts on this subject based on the ideXlab platform.
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high spectral efficiency 114 gb s transmission using polmux rz 8psk modulation format and single ended digital coherent detection technique
Journal of Lightwave Technology, 2009Co-Authors: Xiang Zhou, Jianjun Yu, Dayou Qian, Ting Wang, Guodong Zhang, Peter MagillAbstract:Employing spectrally efficient PolMux-RZ-8PSK modulation format and single-ended digital coherent detection technique, we demonstrate 8 times 114-Gb/s DWDM transmission over 640 km of SSMF on a 25-GHz grid with record spectral efficiency of 4.2 bit/s/Hz, utilizing no optical dispersion compensation or Raman amplification. We show that the distortion caused by the direct square-law detection of the Signal Component with single-ended photo detection can be effectively mitigated by a novel DSP algorithm.
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high spectral efficiency 114 gb s transmission using polmux rz 8psk modulation format and single ended digital coherent detection technique
OFC NFOEC 2008, 2009Co-Authors: Xiang Zhou, Jianjun Yu, Dayou Qian, Ting Wang, Guodong Zhang, Peter MagillAbstract:-Employing spectrally efficient PolMux.RZ.8PSK modulation format and single-ended digital coherent detection technique, we demonstrate 8 x 114-Gb/s DWDM transmission over 640 km of SSMF on a 25-GHz grid with record spectral efficiency of 4.2 bit/s/Hz, utilizing no optical dispersion compensation or Raman amplification. We show that the distortion caused by the direct square-law detection of the Signal Component with single-ended photo detection can be effectively mitigated by a novel DSP algorithm.
Tsan-wen Chen - One of the best experts on this subject based on the ideXlab platform.
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A low power all-digital Signal Component separator for uneven multi-level LINC systems
2011 Proceedings of the ESSCIRC (ESSCIRC), 2011Co-Authors: Tsan-wen Chen, Ping-yuan Tsai, Dieter De Moitie, Jui-yuan YuAbstract:This paper presents an all-digital Signal Component separator (SCS) with low power overhead for uneven multilevel LINC (UMLINC) systems, including a multi-level phase calculator (MLPC) and a digitally-control phase shifter (DCPS) pair. The optimal gain level with branch mismatch consideration is proposed to achieve maximal average efficiency 44.82%. This SCS chip is manufactured in 90 nm standard CMOS process with an active area 0.5 mm2. The required phases of branch Signals and PA gain controls can be calculated by the proposed MLPC. Instead of four DACs, the DCPS pair with a continuous PVT monitor is also proposed to generate the phase-modulated Signals accurately at IF frequency 80 MHz with 8-bit resolution. By applying voltage scaling and source gating on DSP functions and DCPSs respectively, 81.32% power cost of SCS can be reduced, and the overall power is only 0.65 mW. With the proposed SCS, the EVM of -31.06 dB using 64-QAM OFDM Signals can be achieved for high-efficiency UMLINC systems.
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A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters
IEEE Journal of Solid-State Circuits, 2011Co-Authors: Tsan-wen Chen, Ping-yuan Tsai, Jui-yuan YuAbstract:Linear amplification with nonlinear Components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital Signal Component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06 mm2. The DCPS can generate phase-modulated Signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34°). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 μW which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15° phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10° phase mismatch, the system EVM of - 29.81 dB and ACPR of - 34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM Signals.
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A low-power all-digital Signal Component separator for OFDM LINC systems
The 2010 International Conference on Green Circuits and Systems, 2010Co-Authors: Tsan-wen Chen, Ping-yuan Tsai, Jui-yuan YuAbstract:LINC can achieve linear amplification by using high-efficiency amplifiers. This work presents an all-digital LINC Signal Component separator (SCS) including the phase calculation digital Signal processing and two digital-control phase shifters (DCPSs). With the duplicate DCPSs, a pre-calibration scheme is introduced to guarantee the codeword-to-phase linearity and accuracy under different PVT conditions. The proposed DCPS design provides 8-bit resolution at 100 MHz with RMS error 10 ps (0.36°) resulting in system EVM -29.21 dB with 64-QAM OFDM Signals, and the performance can meet the requirements specified in IEEE 802.11a. This work is implemented in a 90 nm CMOS process. With the voltage scaling scheme to specific power domains and the low-complexity DCPS design, the overall SCS consumes 850.51 μW from 0.5 V and 1.0 V supplies.
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A sub-mW all-digital Signal Component separator with branch mismatch compensation for OFDM LINC transmitters
2010 IEEE Asian Solid-State Circuits Conference, 2010Co-Authors: Tsan-wen Chen, Ping-yuan Tsai, Jui-yuan YuAbstract:This paper presents a sub-mW all-digital Signal Component separator (SCS) with a novel branch mismatch compensation scheme for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. This chip is manufactured in 90nm standard CMOS process with active area 0.06mm2. The DCPS can generate phase-modulated Signal at IF 100MHz with 8-bit resolution and RMS error 9.33ps (0.34°). The phase calculation can be operated with maximum 50MHz speed at 0.5V supply voltage, resulting in 73.88% power reduction, and the overall SCS power is only 949.5μW. With the aid of this SCS, the branch mismatch compensation scheme provides 0.02dB gain and 0.15° phase fine-tune resolution. The system EVM with 64-QAM OFDM Signals is -29.81dB, and the spectrum can pass the mask test of IEEE 802.11a.
L. Sundstrom - One of the best experts on this subject based on the ideXlab platform.
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Implementation of the Signal Component generator of a CALLUM 2 transmitter architecture in CMOS technology
Proceedings Norchip Conference 2004., 2004Co-Authors: R. Strandberg, P. Andreani, L. SundstromAbstract:This article presents an analog implementation of the Signal Component generator (SCG) of the CALLUM 2 linear transmitter architecture. The proposed SCG is suited for integration in a standard 0.35 μ m CMOS process, and has from simulations proven to be adequate when operating on an EDGE modulated baseband Signal with a data rate of 270.833 ksymb/s. The total current consumption of the SCG is 2.0mA from a 3.3 V supply. A variable gain amplifier (VGA) with common-mode (CM) control is presented, and the VGA is inserted in between the SCG and the voltage-controlled oscillator (VCO) to adjust the loop gain, which has strong influence on the stability and spectral performance of the linear transmitter architecture.
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An IF CMOS Signal Component separator chip for LINC transmitters
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169), 2001Co-Authors: L. SundstromAbstract:The LINC transmitter provides linear amplification using highly nonlinear but power efficient amplifiers. The Signal Component separator (SCS) is a crucial function of LINC. This paper presents an IF SCS chip implemented in a 0.35 /spl mu/m CMOS process using a design based on voltage-translinear circuits. The experimental LINC transmitter, built with the chip and nonlinear amplifiers, had output spurious levels some -55 dBc and -48 dBc for a NADC Signal and an IS-95 Signal, respectively. This implies a high degree of linearity.
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A LINC transmitter using a new Signal Component separator architecture
VTC2000-Spring. 2000 IEEE 51st Vehicular Technology Conference Proceedings (Cat. No.00CH37026), 2000Co-Authors: L. SundstromAbstract:The LINC (LInear amplification with Nonlinear Components) transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. The Signal Component separator (SCS) is a crucial Signal processing function of LINC. DSP implementation of the SCS at baseband has so far been assumed to be the best choice although it suffers from matching and power consumption problems. A new SCS architecture based on analog integrated circuit (IC) techniques is presented to avoid the problems faced by a DSP-based realization. The proposed scheme is studied at system level by both analysis and simulation. Experimental results are also obtained from a 200 MHz experimental LINC transmitter built around a full-custom analog IC that implements the SCS using this new architecture. Test results showed that spurious levels around -50 dBc could be obtained with a /spl pi//4-shifted DQPSK modulated North American Digital Cellular (NADC) Signal. This implies a high degree of linearity.
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A 200-MHz IF BiCMOS Signal Component separator for linear LINC transmitters
IEEE Journal of Solid-State Circuits, 2000Co-Authors: L. SundstromAbstract:The linear amplification with nonlinear Components (LINC) transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. The Signal Component separator (SCS) is a crucial Signal processing function of LINC. It forms two constant-amplitude phase-modulated Signal Components from the input Signal. Due to the nonlinear Signal processing involved, digital Signal processing (DSP) implementation of the SCS at baseband has so far been assumed to be the best choice although it suffers from matching, bandwidth and power consumption problems. In this paper a new SCS architecture based on analog integrated circuit techniques is presented to avoid the disadvantages in a DSP based realization. A 200-MHz IF SCS chip using the proposed architecture was designed and fabricated in a 0.8 /spl mu/m BiCMOS process. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that spurious levels around -50 dBc could be obtained with a /spl pi//4-shifted DQPSK modulated North American Digital Cellular (NADC) Signal. This implies a high degree of linearity in the implemented LINC transmitter.
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The effect of quantization in a digital Signal Component separator for LINC transmitters
IEEE Transactions on Vehicular Technology, 1996Co-Authors: L. SundstromAbstract:Spectrally efficient modulation schemes have been chosen for the second generation of cellular systems in the United States and Japan, as well as for private mobile radio (PMR) systems. This paper analyzes the effect of quantization in a digital Signal Component separator (SCS) for linear amplification with nonlinear Components (LINC) transmitters. The analysis relies on the fact that the two Signal Components can be obtained as the source Signal plus/minus a Signal in quadrature to the source Signal. The equations derived are vital because they allow the designer to optimize digital Signal processor (DSP) power consumption and bandwidth. The word lengths that are required for the source Signal and the quadrature Signal can be calculated from the amplifier gain characteristic, the probability density function for the modulation scheme, and the specified adjacent channel interference (ACI). The validity of the analysis has been verified by means of simulations.
