The Experts below are selected from a list of 2772 Experts worldwide ranked by ideXlab platform
C Acar - One of the best experts on this subject based on the ideXlab platform.
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nth order current transfer function synthesis using current differencing buffered amplifier Signal Flow Graph approach
Microelectronics Journal, 2000Co-Authors: C Acar, S OzoǧuzAbstract:The authors present a general synthesis method for the realisation of nth-order current transfer function using current differencing buffered amplifier which can easily be derived from a commercially available active component, AD844. The use of this active component simplifies the implementation of analogue Signal processing filters and hence makes the proposed circuit attractive.
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high order voltage transfer function synthesis using ccii based unity gain current amplifiers
Electronics Letters, 1996Co-Authors: C Acar, Serdar OzoguzAbstract:Using the Signal-Flow Graph approach, a general synthesis method for the realisation of high-order voltage transfer functions is presented and a current conveyor filter is obtained. The resulting filter contains a minimum number of capacitors, at most 2n+3 resistors, as well as n+2 current conveyors of plus type, all of which operate in current-mode.
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nth order voltage transfer function synthesis using a commercially available active component Signal Flow Graph approach
Electronics Letters, 1996Co-Authors: C AcarAbstract:The author presents a general synthesis method for the realisation of an nth-order voltage transfer function using an active RC circuit comprising a commercially available active component, AD844, which is equivalent to the combination of a second generation current conveyor having a gain of +1 (CCII+) and a unity gain voltage buffer. The use of this active component simplifies the implementation, making the proposed circuit attractive.
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nth order lowpass voltage transfer function synthesis using ccii s Signal Flow Graph approach
Electronics Letters, 1996Co-Authors: C AcarAbstract:A general synthesis method is given for the realisation of an nth-order lowpass voltage transfer function, using the active RC circuit containing a minimum number of capacitors and n+1 current conveyors at most. All the current conveyors are of the noninverting type, and they act as voltage followers. This makes the proposed circuit simple and attractive.
Mummadi Veerachary - One of the best experts on this subject based on the ideXlab platform.
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Signal Flow Graph modelling of multi state boost dc dc converters
IEE Proceedings - Electric Power Applications, 2004Co-Authors: Mummadi VeeracharyAbstract:A systematic procedure and guidelines for developing the unified Flow Graph model of a multi-state boost DC-DC converter is presented. From this unified model it is possible to predetermine the complete behaviour of the converter system. The proposed method provides ease of model formulation and avoids the mathematical complexity involved in obtaining the unified model. Usefulness of the proposed method is demonstrated through an example of three state boost converters. A simplified procedure is described that can be used to deduce large-Signal, small-Signal and steady-state from the unified Signal Flow Graph of the converter. Large-Signal models models have been developed and programmed in the TUTSIM simulator. Large-Signal responses against supply and load disturbances were obtained. Theoretical results, obtained from the proposed Signal Flow Graph method, are compared with PSIM power electronic simulator results. Experimental results are provided to validate the proposed modelling method.
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general rules for Signal Flow Graph modeling and analysis of dc dc converters
IEEE Transactions on Aerospace and Electronic Systems, 2004Co-Authors: Mummadi VeeracharyAbstract:Signal Flow Graph (SFG) nonlinear modeling approach is well known for modeling dc-dc converters. However, all possible SFGs of a given dc-dc converter system will not yield the generalized Graph. A systematic procedure and guidelines for developing unified Flow Graph models of the dc-dc boost converters, from which complete behavior can be determined is presented. Usefulness of the proposed method is demonstrated through examples. As an illustration a 2-cell cascade boost and interleaved boost converter systems are taken as examples. Derivation of large, small-Signal and steady-state models from generalized Flow Graph is also demonstrated. Large-Signal model is developed and programmed in TUTSIM simulator. Large-Signal, responses against supply and load disturbances are obtained. Experimental observations are provided to validate the proposed algorithm.
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Analysis of interleaved dual boost converter with integrated magnetics: Signal Flow Graph approach
IEE Proceedings - Electric Power Applications, 2003Co-Authors: Mummadi VeeracharyAbstract:A systematic development of a unified Signal Flow Graph model for an interleaved boost converter with coupled inductor system operating in continuous current mode is presented. This Signal Flow Graph approach provides a means to directly translate the switching converter to its Graphic model, from which steady-state and dynamic behaviour of the converter can easily be studied. Development of a unified Signal Flow Graph is explained and derivation of large, small-Signal and steady-state models is demonstrated. Converter performance expressions such as steady-state voltage gain, efficiency expressions and small-Signal characteristic transfer functions are also derived. Large-Signal responses against supply and load disturbances are predicted by programming the corresponding Signal Flow Graph in the TUTSIM simulator. Experimental observations are provided to validate the Signal Flow Graph modelling method. Frequency response characteristics generated from the Signal Flow method are validated with PSpice simulations. Further, the mathematical models obtained from the Signal Flow Graph modelling are in agreement with those obtained from the state-space averaging technique.
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Voltage-based maximum power point tracking control of PV system
IEEE Transactions on Aerospace and Electronic Systems, 2002Co-Authors: Mummadi Veerachary, Tomonobu Senjyu, Katsumi UezatoAbstract:Photovoltaic (PV) generators exhibit nonlinear v-i characteristics and maximum power (MP) points that vary with solar insolation. An intermediate converter can therefore increase efficiency by matching the PV system to the load and by operating the solar cell arrays (SCAs) at their maximum power point. An MP point tracking algorithm is developed using only SCA voltage information thus leading to current sensorless tracking control. The inadequacy of a boost converter for array voltage based MP point control is experimentally verified and an improved converter system is proposed. The proposed converter system results in low ripple content, which improves the array performance and hence a lower value of capacitance is sufficient on the solar array side. Simplified mathematical expressions for a PV source are derived. A Signal Flow Graph is employed for modeling the converter system. Current sensorless peak power tracking effectiveness is demonstrated through simulation results. Experimental results are presented to validate the proposed method.
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Signal Flow Graph nonlinear modelling of interleaved converters
IEE Proceedings - Electric Power Applications, 2001Co-Authors: Mummadi Veerachary, Tomonobu Senjyu, Katsumi UezatoAbstract:This paper presents a systematic development of a unified Signal Flow Graph (SFG) model for an N-cell interleaved DC-DC converter system operating in continuous current mode. From this SFG small, large-Signal and steady-state models are developed, which are useful to study the converter behaviour. Converter performance expressions like voltage gain, efficiency and other small-Signal transfer functions are derived. A straightforward algorithm is developed to draw the unified SFG of an N-cell interleaved converter system without going into the rigorous procedure. Development of a unified Signal Flow Graph is explained for a 3-cell interleaved converter system. Derivation of large, small-Signal and steady-state models from the unified SFG is demonstrated by considering a 2-cell interleaved converter system. A large-Signal model is programmed in a TUTSIM simulator, and the large-Signal responses against supply, load disturbances are predicted. Signal Flow Graph analysis results are validated with PSIM simulations. Experimental observations are provided to validate the SFG modelling method.
W. Surakampontorn - One of the best experts on this subject based on the ideXlab platform.
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efficient implementation of tunable ladder filters using multi output current controlled conveyors
Aeu-international Journal of Electronics and Communications, 2008Co-Authors: Amorn Jirasereeamornkun, W. SurakampontornAbstract:Abstract A methodology to realize continuous-time current-mode tunable ladder filters of any order has been presented. This proposed technique individually simulates Signal Flow Graph (SFG) of each branch element from passive filter prototype using only multi-output second generation current controlled conveyors (MCCCIIs) and grounded capacitors. This leads to simple structure, ease of design and suitability for IC fabrication. A third-order Butterworth low-pass filter, a third-order elliptic low-pass filter and a sixth-order Chebyshev band-pass filter are employed to demonstrate the proposed realization scheme. These simulated filters retain minimum requirement of passive and active elements and provide the filter corner frequency tunability. Moreover, the method allows an implementation of the elliptic filters by simply adding floating capacitors to all-pole filter structures.
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efficient implementation of tunable ladder filters using multi output current controlled conveyors
Aeu-international Journal of Electronics and Communications, 2008Co-Authors: Amorn Jirasereeamornkun, W. SurakampontornAbstract:A methodology to realize continuous-time current-mode tunable ladder filters of any order has been presented. This proposed technique individually simulates Signal Flow Graph (SFG) of each branch element from passive filter prototype using only multi-output second generation current controlled conveyors (MCCCIIs) and grounded capacitors. This leads to simple structure, ease of design and suitability for IC fabrication. A third-order Butterworth low-pass filter, a third-order elliptic low-pass filter and a sixth-order Chebyshev band-pass filter are employed to demonstrate the proposed realization scheme. These simulated filters retain minimum requirement of passive and active elements and provide the filter corner frequency tunability. Moreover, the method allows an implementation of the elliptic filters by simply adding floating capacitors to all-pole filter structures. 2007 Elsevier GmbH. All rights reserved.
A A Abidi - One of the best experts on this subject based on the ideXlab platform.
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fet r c circuits a unified treatment part ii extension to multi paths noise figure and driving point impedance
IEEE Transactions on Circuits and Systems, 2016Co-Authors: Tetsuya Iizuka, A A AbidiAbstract:In Part I of this paper, we introduce useful analysis that leads to a simple Signal Flow Graph (SFG), which captures the FET-R-C circuit's action completely across a wide range of design parameters. Part I focuses on the analysis of a single-path FET-R-C circuit's Signal transfer characteristics and gives us guidelines for sample-and-hold (S/H) and passive sampling mixer (P-M) designs. Part II extends the analysis to multi-path FET-R-C circuit configurations, e.g., a complex $I$ - $Q$ passive mixer that is common in RF applications. Then the noise and driving-point impedance analyses are carried out to provide valuable insights of practical S/H and P-M designs.
Swapna Banerjee - One of the best experts on this subject based on the ideXlab platform.
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an efficient architecture for 3 d discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology, 2010Co-Authors: A Das, A Hazra, Swapna BanerjeeAbstract:This paper presents an architecture of the lifting-based running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3-D-DWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting Signal Flow Graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput compared to those of earlier reported works. The proposed architecture has been successfully implemented on Xilinx Virtex-IV series field-programmable gate array, offering a speed of 321 MHz, making it suitable for real-time compression even with large frame dimensions. Moreover, the architecture is fully scalable beyond the present coherent Daubechies filterbank (9, 7).