The Experts below are selected from a list of 5199 Experts worldwide ranked by ideXlab platform
Kenneth P. Parker - One of the best experts on this subject based on the ideXlab platform.
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The Boundary-Scan Handbook
2016Co-Authors: Kenneth P. ParkerAbstract:Boundary-Scan Basics And Vocabulary.- Boundary-Scan Description Language (BSDL) -- Boundary-Scan Testing -- Advanced Boundary-Scan Topics -- Design for Boundary-Scan Test -- Analog Measurement Basics -- IEEE 1149.4 Analog Boundary-Scan.- IEEE 1149.6 Testing Advanced I/O.- IEEE 1532:In-System Configuration -- IEEE 1149.8.1: Passive Components -- IEEE 1149.1:The 2013 Revision.- IEEE 1149.6: The 2015 Revision.
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Boundary-Scan Testing
The Boundary-Scan Handbook, 2016Co-Authors: Kenneth P. ParkerAbstract:Boundary-Scan testing is aimed primarily at digital logic structures, although Boundary-Scan assets can provide invaluable resources for assisting with mixed digital/analog testing as well. This chapter covers various test approaches utilizing 1149.1.
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The Boundary-Scan Handbook
2016Co-Authors: Kenneth P. ParkerAbstract:Aimed at electronics industry professionals, this 4th edition of the Boundary Scan Handbook describes recent changes to the IEEE1149.1 Standard Test Access Port and Boundary-Scan Architecture. This updated edition features new chapters on the possible effects of the changes on the work of the practicing test engineers and the new 1149.8.1 standard. Anyone needing to understand the basics of Boundary Scan and its practical industrial implementation will need this book. Provides an overview of the recent changes to the 1149.1 standard and the effect of the changes on the work of test engineers; Explains the new IEEE 1149.8.1 subsidiary standard and applications; Describes the latest updates on the supplementary IEEE testing standards. In particular, addresses: IEEE Std 1149.1 Digital Boundary-Scan IEEE Std 1149.4 Analog Boundary-Scan IEEE Std 1149.6 Advanced I/O Testing IEEE Std 1149.8.1 Passive Component Testing IEEE Std 1149.1-2013 The 2013 Revision of 1149.1 IEEE Std 1532 In-System Configuration IEEE Std 1149.6-2015 The 2015 Revision of 1149.6
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IEEE 1149.4: Analog Boundary-Scan
The Boundary-Scan Handbook, 2016Co-Authors: Kenneth P. ParkerAbstract:IEEE Standard 1149.4 [IEEE99] is titled “Mixed Signal Test Bus” but has become known popularly as “Analog Boundary-Scan”. It is natural to ask, what is “Analog Boundary-Scan”? The digital paradigm we have been using is confusing when we hear the word analog. Could it mean we somehow capture analog voltages and somehow shift them out for viewing (as proposed in [Wagn88])? The answer is “no”. The simplest concept of the 1149.4 Standard is to imagine that we have integrated a portion of an ATE system’s analog measurement bus and multiplexing system into an IC, eliminating the need for bed-of-nails access to it. Since these test resources have been converted from discrete relays, wire wrap and nails into silicon, they will scale with silicon technology as it continues to shrink.
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The Boundary-Scan Handbook
2013Co-Authors: Kenneth P. ParkerAbstract:Boundary-Scan, formally known as IEEE/ANSI Standard 1149.1-1990, is a collection of design rules applied principally at the integrated circuit (IC) level that allow software to alleviate the growing cost of designing and producing digital systems. The primary benefit of the standard is its ability to transform extremely printed circuit board testing problems that could only be attacked with ad-hoc testing methods into well-structured problems that software can easily and swiftly deal with. The Boundary-Scan Handbook is for professionals in the electronics industry who are concerned with the practical problems of competing successfully in the face of rapid-fire technological change. Since many of these changes affect our ability to do testing and hence cost-effective production, the advent of the 1149.1 standard is rightly looked upon as a major breakthrough. However, there is a great deal of misunderstanding about what to expect of 1149.1 and how to use it. Because of this, The Boundary-Scan Handbook is not a rehash of the 1149.1 standard, nor does it intend to be a tutorial on the basics of its workings. The standard itself should always be consulted for this, being careful to follow supplements issued by the IEEE that clarify and correct it. Rather, The Boundary-Scan Handbook motivates proper expectations and explains how to use the standard successfully.
Kuen-jong Lee - One of the best experts on this subject based on the ideXlab platform.
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Boundary Scan and core-based testing
VLSI Test Principles and Architectures, 2007Co-Authors: Kuen-jong LeeAbstract:Publisher Summary Boundary Scan, also known as the IEEE or JTAG standard, appears to be the most successful test standard ever approved by the IEEE. This chapter focuses on the 1149.1, 1149.6, and 1500 test standards. Test architectures to support these standards are also reviewed in the chapter. Currently, Boundary Scan is widely used throughout the industry; most commercial computer-aided test tools provide automatic synthesis capability for Boundary-Scan design. This chapter introduces the Boundary-Scan family of standards and their current status. The 1149.1 standard is then described in detail. On-chip design to support Scan and BIST by 1149.1 and board or system-level controller design for 1149.1 is also briefly addresses in the chapter. It also presents test control architectures to support 1500 design with the plug-and-play feature and hierarchical test structures. This chapter concludes by discussing a comparison between 1149.1 and 1500.
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Analogue Boundary Scan architecture for DC and AC testing
Electronics Letters, 1996Co-Authors: Kuen-jong Lee, Tian-pao Lee, Rong-chang Wen, Zhe-yi LinAbstract:A new mixed-mode Boundary Scan architecture is developed. The digital part of this architecture complies with the IEEE Std 1149.1. For the analogue part, we propose a new Boundary Scan cell design and define four analogue test instructions. The control signals for each instruction are also described.
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ISCAS - A new architecture for analog Boundary Scan
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 1995Co-Authors: Kuen-jong Lee, Sheng-yih Jeng, Tian-pao LeeAbstract:The IEEE Boundary Scan Standard 1149.1 has been widely used for digital circuit testing. A similar standard for analog circuits is yet to be set up. In this paper we propose a new analog Boundary Scan architecture which is similar to the IEEE Std. 1149.1. The basic analog Boundary Scan cell, the defined instructions, the associated operations, and the control circuitry are described. The advantages of this architecture include: (1) Signal at various test points can be sampled simultaneously, (2) test stimuli can be injected to various test points simultaneously, and (3) test stimuli loading and test response outputting can be done simultaneously.
G. D. Robinson - One of the best experts on this subject based on the ideXlab platform.
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Basic Boundary-Scan for in-circuit test
Proceedings ETC 93 Third European Test Conference, 1993Co-Authors: A.j. Albee, M Ellis, G. D. RobinsonAbstract:Boundary-Scan was developed to allow testing without a full bed-of-nails, but many boards have only a few Boundary-Scan parts, and still require a full bed-of-nails. The manufacturers of those boards are getting many advantages from the use of Boundary-Scan, including faster model development time for complex parts, faster test run times, faster model and board debug times and much more accurate diagnosis than a conventional in-circuit test provides. This paper describes a tool that provides these benefits without needing any change to the main in-circuit test system. >
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interconnect testing of boards with partial Boundary Scan
International Test Conference, 1990Co-Authors: G. D. Robinson, J G DeshayesAbstract:It is shown that interconnect testing for boards that mix Boundary Scan and conventional components can be performed effectively by a four-stage strategy: a conventional shorts test where the tester has access, a Scan circuitry integrity test, a fairly conventional Boundary Scan interconnect test, and a test for shorts between the Boundary Scan and conventional parts of the circuit, which is new. There are a number of complications so that careful analysis of the results is needed, even for the conventional parts of the test, but this strategy can be used to give a precise, usable diagnosis of the problems. It is noted that a circuit is not necessarily testable just because it contains Boundary Scan parts. The test access port on those components is a potential weak link, and physical access to those signals is necessary to get good diagnosis. In addition, it may be impossible to diagnose accurately shorts involving nodes with neither physical access nor Boundary Scan access, and that may even repeatedly not be detectable. >
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ITC - Interconnect testing of boards with partial Boundary Scan
Proceedings. International Test Conference 1990, 1990Co-Authors: G. D. Robinson, J G DeshayesAbstract:It is shown that interconnect testing for boards that mix Boundary Scan and conventional components can be performed effectively by a four-stage strategy: a conventional shorts test where the tester has access, a Scan circuitry integrity test, a fairly conventional Boundary Scan interconnect test, and a test for shorts between the Boundary Scan and conventional parts of the circuit, which is new. There are a number of complications so that careful analysis of the results is needed, even for the conventional parts of the test, but this strategy can be used to give a precise, usable diagnosis of the problems. It is noted that a circuit is not necessarily testable just because it contains Boundary Scan parts. The test access port on those components is a potential weak link, and physical access to those signals is necessary to get good diagnosis. In addition, it may be impossible to diagnose accurately shorts involving nodes with neither physical access nor Boundary Scan access, and that may even repeatedly not be detectable. >
J G Deshayes - One of the best experts on this subject based on the ideXlab platform.
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interconnect testing of boards with partial Boundary Scan
International Test Conference, 1990Co-Authors: G. D. Robinson, J G DeshayesAbstract:It is shown that interconnect testing for boards that mix Boundary Scan and conventional components can be performed effectively by a four-stage strategy: a conventional shorts test where the tester has access, a Scan circuitry integrity test, a fairly conventional Boundary Scan interconnect test, and a test for shorts between the Boundary Scan and conventional parts of the circuit, which is new. There are a number of complications so that careful analysis of the results is needed, even for the conventional parts of the test, but this strategy can be used to give a precise, usable diagnosis of the problems. It is noted that a circuit is not necessarily testable just because it contains Boundary Scan parts. The test access port on those components is a potential weak link, and physical access to those signals is necessary to get good diagnosis. In addition, it may be impossible to diagnose accurately shorts involving nodes with neither physical access nor Boundary Scan access, and that may even repeatedly not be detectable. >
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ITC - Interconnect testing of boards with partial Boundary Scan
Proceedings. International Test Conference 1990, 1990Co-Authors: G. D. Robinson, J G DeshayesAbstract:It is shown that interconnect testing for boards that mix Boundary Scan and conventional components can be performed effectively by a four-stage strategy: a conventional shorts test where the tester has access, a Scan circuitry integrity test, a fairly conventional Boundary Scan interconnect test, and a test for shorts between the Boundary Scan and conventional parts of the circuit, which is new. There are a number of complications so that careful analysis of the results is needed, even for the conventional parts of the test, but this strategy can be used to give a precise, usable diagnosis of the problems. It is noted that a circuit is not necessarily testable just because it contains Boundary Scan parts. The test access port on those components is a potential weak link, and physical access to those signals is necessary to get good diagnosis. In addition, it may be impossible to diagnose accurately shorts involving nodes with neither physical access nor Boundary Scan access, and that may even repeatedly not be detectable. >
Robert Sedevčič - One of the best experts on this subject based on the ideXlab platform.
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Linux-based experimental Boundary Scan environment
Microprocessors and microsystems, 2016Co-Authors: Franc Novak, Uroš Kač, Anton Biasizzo, Robert SedevčičAbstract:This paper presents the implementation of a Linux-based experimental Boundary Scan environment. Its primary aim is to provide a flexible and completely open platform to people interested in experimenting with IEEE 1149.x and related standards and allow them to develop custom applications requiring Boundary Scan infrastructure control capabilities. The experimental Boundary Scan test platform is based on readily available hardware components and on the Linux operating system. An ISA-bus to IEEE 1149.1 test bus PC adapter, supporting various Boundary Scan chain configurations, and a flexible Linux device driverhave been implemented so far. They form the core of the test platform, allowing the development of more complex Boundary Scan test applications.
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Experimental Boundary-Scan environment for research and education
First International Workshop onTestability Assessment 2004. IWoTA 2004. Proceedings., 2004Co-Authors: Robert Sedevčič, Uroš Kač, Franc Novak, Anton BiasizzoAbstract:The paper presents the experimental Boundary-Scan (EBS) environment, a pedagogical tool for research and education in the area of electronic test. The EBS environment was conceived primarily as a simple laboratory test system and a basic teaching aid for the IEEE 1149.x family of testability standards. It is based on a widely available hardware supporting Boundary-Scan test techniques and on the open source Linux operating system.
