Silicon Layer

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Banshi D Gupta - One of the best experts on this subject based on the ideXlab platform.

  • sensitivity enhancement of a surface plasmon resonance based biomolecules sensor using graphene and Silicon Layers
    Sensors and Actuators B-chemical, 2011
    Co-Authors: Roli Verma, Banshi D Gupta
    Abstract:

    Abstract A surface plasmon resonance based biomolecules sensor using Silicon and graphene Layers coated over the base of the high index prism sputtered with gold has been analyzed. The graphene Layer has been used to enhance the adsorption of biomolecules while the addition of Silicon Layer between gold and graphene increases the sensitivity. The thicknesses of gold and Silicon Layers along with the number of graphene Layers have been optimized to achieve the best performance of the sensor in terms of sensitivity and Full Width at Half Maximum (FWHM). To see the effect of wavelength of the light source, simulations have been carried out for three different wavelengths. The best performance is obtained for 633 nm wavelength with optimized thicknesses of gold and Silicon Layers as 40 nm and 7 nm respectively while the optimum number of graphene Layers is 2. The sensitivity obtained with optimized parameters and additional Silicon Layer, is more than twice the value reported in the literature.

  • surface plasmon resonance based fiber optic refractive index sensor sensitivity enhancement
    Applied Optics, 2011
    Co-Authors: Priya Bhatia, Banshi D Gupta
    Abstract:

    We have experimentally studied the surface plasmon resonance (SPR)-based fiber-optic refractive index sensor incorporating a high-index dielectric Layer using the wavelength interrogation method. Silver and gold have been used as SPR active metals followed by a high-index dielectric Layer of Silicon. Experimental results predict a redshift in the resonance wavelength with the increase in the refractive index of the sensing Layer for a given thickness of the Silicon Layer. Further, as the thickness of the Silicon Layer increases, the sensitivity of the sensor increases. The upper limit of the Silicon film thickness for the enhancement of the sensitivity has been found to be around 10 nm. The experimental results obtained on sensitivity match qualitatively with the theoretical results obtained using the N-Layer model and the ray approach. The increase in sensitivity is due to the increase in the electric field intensity at the Silicon-sensing-region interface. In addition to an increase in sensitivity, the Silicon Layer can be used to tune the resonance wavelength and can protect the metal Layer from oxidation and hence can improve the durability of the probe.

T Y Tan - One of the best experts on this subject based on the ideXlab platform.

  • a smarter cut approach to low temperature Silicon Layer transfer
    Applied Physics Letters, 1998
    Co-Authors: Qinyi Tong, R Scholz, U Gosele, T H Lee, L J Huang, Yulin Chao, T Y Tan
    Abstract:

    Silicon wafers were first implanted at room temperature by B+ with 5.0×1012 to 5.0×1015 ions/ cm2 at 180 keV, and subsequently implanted by H2+ with 5.0×1016 ions/cm2 at an energy which locates the H-peak concentration in the Silicon wafers at the same position as that of the implanted boron peak. Compared to the H-only implanted samples, the temperature for a B+H coimplanted Silicon Layer to split from its substrate after wafer bonding during a heat treatment for a given time is reduced significantly. Further reduction of the splitting temperature is accomplished by appropriate prebonding annealing of the B+H coimplanted wafers. Combination of these two effects allows the transfer of a Silicon Layer from a Silicon wafer onto a severely thermally mismatched substrate such as quartz at a temperature as low as 200 °C.

  • A “smarter-cut” approach to low temperature Silicon Layer transfer
    Applied Physics Letters, 1998
    Co-Authors: Qinyi Tong, R Scholz, U Gosele, T H Lee, L J Huang, Yulin Chao, T Y Tan
    Abstract:

    Silicon wafers were first implanted at room temperature by B+ with 5.0×1012 to 5.0×1015 ions/ cm2 at 180 keV, and subsequently implanted by H2+ with 5.0×1016 ions/cm2 at an energy which locates the H-peak concentration in the Silicon wafers at the same position as that of the implanted boron peak. Compared to the H-only implanted samples, the temperature for a B+H coimplanted Silicon Layer to split from its substrate after wafer bonding during a heat treatment for a given time is reduced significantly. Further reduction of the splitting temperature is accomplished by appropriate prebonding annealing of the B+H coimplanted wafers. Combination of these two effects allows the transfer of a Silicon Layer from a Silicon wafer onto a severely thermally mismatched substrate such as quartz at a temperature as low as 200 °C.

L Miglio - One of the best experts on this subject based on the ideXlab platform.

  • Strain in a single ultrathin Silicon Layer on top of SiGe islands: Raman spectroscopy and simulations
    Physical Review B, 2009
    Co-Authors: Emiliano Bonera, Fabio Pezzoli, A. Picco, G. Vastola, Mathieu Stoffel, Emanuele Grilli, Mario Guzzi, Armando Rastelli, Oliver G. Schmidt, L Miglio
    Abstract:

    By means of resonant Raman spectroscopy we investigated the strain on a single ultrathin crystalline Silicon Layer, locally induced by buried SiGe nanostructures. The spectrum of a 5-nm-thick Silicon Layer on top of SiGe islands shows a single highly strained feature attributed to the out-of-plane phonon. The direct comparison of the experimental results with finite-element methods through spectral simulation shows excellent agreement that clarifies the physical origin of the spectrum. An increase in the Silicon Layer thickness up to 40 nm results in a progressive reduction in the strain.

E. D. Jones - One of the best experts on this subject based on the ideXlab platform.

U Gosele - One of the best experts on this subject based on the ideXlab platform.

  • a smarter cut approach to low temperature Silicon Layer transfer
    Applied Physics Letters, 1998
    Co-Authors: Qinyi Tong, R Scholz, U Gosele, T H Lee, L J Huang, Yulin Chao, T Y Tan
    Abstract:

    Silicon wafers were first implanted at room temperature by B+ with 5.0×1012 to 5.0×1015 ions/ cm2 at 180 keV, and subsequently implanted by H2+ with 5.0×1016 ions/cm2 at an energy which locates the H-peak concentration in the Silicon wafers at the same position as that of the implanted boron peak. Compared to the H-only implanted samples, the temperature for a B+H coimplanted Silicon Layer to split from its substrate after wafer bonding during a heat treatment for a given time is reduced significantly. Further reduction of the splitting temperature is accomplished by appropriate prebonding annealing of the B+H coimplanted wafers. Combination of these two effects allows the transfer of a Silicon Layer from a Silicon wafer onto a severely thermally mismatched substrate such as quartz at a temperature as low as 200 °C.

  • A “smarter-cut” approach to low temperature Silicon Layer transfer
    Applied Physics Letters, 1998
    Co-Authors: Qinyi Tong, R Scholz, U Gosele, T H Lee, L J Huang, Yulin Chao, T Y Tan
    Abstract:

    Silicon wafers were first implanted at room temperature by B+ with 5.0×1012 to 5.0×1015 ions/ cm2 at 180 keV, and subsequently implanted by H2+ with 5.0×1016 ions/cm2 at an energy which locates the H-peak concentration in the Silicon wafers at the same position as that of the implanted boron peak. Compared to the H-only implanted samples, the temperature for a B+H coimplanted Silicon Layer to split from its substrate after wafer bonding during a heat treatment for a given time is reduced significantly. Further reduction of the splitting temperature is accomplished by appropriate prebonding annealing of the B+H coimplanted wafers. Combination of these two effects allows the transfer of a Silicon Layer from a Silicon wafer onto a severely thermally mismatched substrate such as quartz at a temperature as low as 200 °C.

  • Growth of buried oxide Layers of Silicon-on-insulator structures by thermal oxidation of the top Silicon Layer
    Journal of The Electrochemical Society, 1997
    Co-Authors: E. Schroer, U Gosele, S. Hopfe, Q.-y. Tong, W. Skorupa
    Abstract:

    We have investigated the thickness increase of buried oxide Layers in Silicon-on-insulator structures by thermal oxidation of the top Silicon Layer. A thermodynamic model is derived based on the experimental observation that oxidation introduces an oxygen concentration into Silicon which is above its solubility limit. Experiments on buried oxide growth by thermal oxidation of the top Silicon Layer were performed with specially designed bond-and-etchback Silicon-on-insulator structures in the temperature range between 1100 and 1200°C. The results obtained are compared to the thermodynamic model and to data from other growth experiments. The different buried oxide growth rates observed for different types of Silicon-on-insulator material are discussed in terms of different Silicon self-interstitial supersaturations which are induced in the top Silicon Layer during oxidation.