The Experts below are selected from a list of 15063 Experts worldwide ranked by ideXlab platform

Sule Ozev - One of the best experts on this subject based on the ideXlab platform.

  • A Multi-Site Test Solution for Quadrature Modulation RF Transceivers
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011
    Co-Authors: Erdem S. Erdogan, Sule Ozev
    Abstract:

    In this letter, we present a 2x-Site Test solution for radio frequency transceivers using only baseband signals for analysis. We perform all operations on communication standard-compliant signal packets, thereby putting the device under the normal operating conditions. The transmitter on one device under Test (DUT) is coupled with a receiver on another DUT to form a complete transmitter-to-receiver path. Parameters of the two devices are decoupled from one another by carefully modeling the system and using signal processing techniques. Simulation as well as measurement results confirm the high accuracy of the proposed technique.

  • A Packet Based 2x-Site Test Solution for GSM Transceivers with Limited Tester Resources
    2009 27th IEEE VLSI Test Symposium, 2009
    Co-Authors: Erdem S. Erdogan, Sule Ozev
    Abstract:

    In this paper, we present a 2x-Site Test solution for GSM transceivers using only baseband signals for analysis. We perform all operations on standard-compliant GSM packets, thereby putting the device under the normal operating conditions. The transmitter on one device under Test (DUT) is coupled with a receiver on another DUT to form a complete Tx-Rx path. Parameters of the two devices are decoupled from one another by carefully modeling the system into a known format and using signal processing techniques. Simulation as well as measurement results confirm the high accuracy of the proposed technique.

Binson Shen - One of the best experts on this subject based on the ideXlab platform.

  • Addressable failure Site Test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation
    IEEE Transactions on Semiconductor Manufacturing, 2001
    Co-Authors: K.y.-y. Doong, Sunnys Hsieh, Binson Shen, Jye-yen Cheng, Ding-ming Kwai, C. Hess, L.h. Weiland
    Abstract:

    As technologies scale down, semiconductor manufacturing processes require more and more areas for Test structures to ensure accurate yield estimation. This paper presents design guidelines for Test structures with addressable failure Sites to efficiently utilize a given area. Different types of Test structures with three-level interconnects are developed and validated using a novel simulation system. Based on the proposed algorithm, single and multiple defects can be detected and identified precisely without ambiguity. The methodology standardizes the design of Test structures for defect capturing as well as their usage within a common pad frame, which can be shared for various processes and applications. A Test chip of 22/spl times/6.6 mm/sup 2/ containing a variety of types of these Test structures was implemented to demonstrate the design feasibility.

  • Addressable failure Site Test structures (AFS-TS) for process development and optimization
    ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095), 2000
    Co-Authors: K.y.-y. Doong, Sunnys Hsieh, Binson Shen, Wang Chien-jung, Yen-hen Ho, Jye-yen Cheng, Yeu-haw Yang, K. Miyamoto
    Abstract:

    Two types of addressable failure Site Test structures are developed. In-house program is coded to extract the electrical information and simulate the failure mode. A complete set of Test structure modules for 0.25 um logic backend of line process is implemented in a Test chip of 22/spl times/6.6 mm/sup 2/. By using the novel Test structure, the yield analysis and defect tracking of BEOL process development as well as low-k Fluorinated SiO/sub 2/ (FSG) process optimization are demonstrated.

  • The short-loop process tuning & yield evaluation by using the addressable failure Site Test structures (AFS-TS)
    Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130), 2000
    Co-Authors: Yih-yuh K. Doong, Sunnys Hsieh, Binson Shen
    Abstract:

    This work describes the implementation of a novel Test structure called addressable failure Site Test structure (AFS-TS) for via process optimization including the liner layer and W-CVD filling process. It manifests the design, defect detection and yield analysis of addressable failure Site Test structures. The novel Test structures are used to discriminate the yield loss issues based on the high spatial defect detection resolution within 2000/spl times/2200 /spl mu/m/sup 2/ of interconnect Test structures. A Test chip of 4.0/spl times/6.6 mm/sup 2/ containing nine types of Test structures was implemented using 0.25 /spl mu/m logic backend of line process. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

Erdem S. Erdogan - One of the best experts on this subject based on the ideXlab platform.

  • A Multi-Site Test Solution for Quadrature Modulation RF Transceivers
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011
    Co-Authors: Erdem S. Erdogan, Sule Ozev
    Abstract:

    In this letter, we present a 2x-Site Test solution for radio frequency transceivers using only baseband signals for analysis. We perform all operations on communication standard-compliant signal packets, thereby putting the device under the normal operating conditions. The transmitter on one device under Test (DUT) is coupled with a receiver on another DUT to form a complete transmitter-to-receiver path. Parameters of the two devices are decoupled from one another by carefully modeling the system and using signal processing techniques. Simulation as well as measurement results confirm the high accuracy of the proposed technique.

  • A Packet Based 2x-Site Test Solution for GSM Transceivers with Limited Tester Resources
    2009 27th IEEE VLSI Test Symposium, 2009
    Co-Authors: Erdem S. Erdogan, Sule Ozev
    Abstract:

    In this paper, we present a 2x-Site Test solution for GSM transceivers using only baseband signals for analysis. We perform all operations on standard-compliant GSM packets, thereby putting the device under the normal operating conditions. The transmitter on one device under Test (DUT) is coupled with a receiver on another DUT to form a complete Tx-Rx path. Parameters of the two devices are decoupled from one another by carefully modeling the system into a known format and using signal processing techniques. Simulation as well as measurement results confirm the high accuracy of the proposed technique.

Sunnys Hsieh - One of the best experts on this subject based on the ideXlab platform.

  • Addressable failure Site Test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation
    IEEE Transactions on Semiconductor Manufacturing, 2001
    Co-Authors: K.y.-y. Doong, Sunnys Hsieh, Binson Shen, Jye-yen Cheng, Ding-ming Kwai, C. Hess, L.h. Weiland
    Abstract:

    As technologies scale down, semiconductor manufacturing processes require more and more areas for Test structures to ensure accurate yield estimation. This paper presents design guidelines for Test structures with addressable failure Sites to efficiently utilize a given area. Different types of Test structures with three-level interconnects are developed and validated using a novel simulation system. Based on the proposed algorithm, single and multiple defects can be detected and identified precisely without ambiguity. The methodology standardizes the design of Test structures for defect capturing as well as their usage within a common pad frame, which can be shared for various processes and applications. A Test chip of 22/spl times/6.6 mm/sup 2/ containing a variety of types of these Test structures was implemented to demonstrate the design feasibility.

  • Addressable failure Site Test structures (AFS-TS) for process development and optimization
    ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095), 2000
    Co-Authors: K.y.-y. Doong, Sunnys Hsieh, Binson Shen, Wang Chien-jung, Yen-hen Ho, Jye-yen Cheng, Yeu-haw Yang, K. Miyamoto
    Abstract:

    Two types of addressable failure Site Test structures are developed. In-house program is coded to extract the electrical information and simulate the failure mode. A complete set of Test structure modules for 0.25 um logic backend of line process is implemented in a Test chip of 22/spl times/6.6 mm/sup 2/. By using the novel Test structure, the yield analysis and defect tracking of BEOL process development as well as low-k Fluorinated SiO/sub 2/ (FSG) process optimization are demonstrated.

  • The short-loop process tuning & yield evaluation by using the addressable failure Site Test structures (AFS-TS)
    Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130), 2000
    Co-Authors: Yih-yuh K. Doong, Sunnys Hsieh, Binson Shen
    Abstract:

    This work describes the implementation of a novel Test structure called addressable failure Site Test structure (AFS-TS) for via process optimization including the liner layer and W-CVD filling process. It manifests the design, defect detection and yield analysis of addressable failure Site Test structures. The novel Test structures are used to discriminate the yield loss issues based on the high spatial defect detection resolution within 2000/spl times/2200 /spl mu/m/sup 2/ of interconnect Test structures. A Test chip of 4.0/spl times/6.6 mm/sup 2/ containing nine types of Test structures was implemented using 0.25 /spl mu/m logic backend of line process. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

  • Novel assessment of process control monitor in advanced semiconductor manufacturing: a complete set of addressable failure Site Test structures (AFS-TS)
    1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No.99CH36314), 1999
    Co-Authors: Sunnys Hsieh, K.y.-y. Doong, Jye-yen Cheng, Jian-rong Wang, Chia-wen Huang, Yu-hao Yang, K. Miyamoto
    Abstract:

    This work describes the implementation of a novel assessment of process control monitor in advanced semiconductor manufacturing. It manifests the design and simulation results of addressable failure Site Test structures. Four novel Test structures with three level interconnects have been developed and validated with an in-house simulation system. The novel Test structures are used to identify the locations of killer defects. A Test chip of 22/spl times/6.6 mm/sup 2/ containing four types Test structures was implemented using a 0.25 /spl mu/m logic backend of line process. This simple and efficient Test structure for killer defect identification demonstrated its superiority in yield enhancement.

K.y.-y. Doong - One of the best experts on this subject based on the ideXlab platform.

  • Addressable failure Site Test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation
    IEEE Transactions on Semiconductor Manufacturing, 2001
    Co-Authors: K.y.-y. Doong, Sunnys Hsieh, Binson Shen, Jye-yen Cheng, Ding-ming Kwai, C. Hess, L.h. Weiland
    Abstract:

    As technologies scale down, semiconductor manufacturing processes require more and more areas for Test structures to ensure accurate yield estimation. This paper presents design guidelines for Test structures with addressable failure Sites to efficiently utilize a given area. Different types of Test structures with three-level interconnects are developed and validated using a novel simulation system. Based on the proposed algorithm, single and multiple defects can be detected and identified precisely without ambiguity. The methodology standardizes the design of Test structures for defect capturing as well as their usage within a common pad frame, which can be shared for various processes and applications. A Test chip of 22/spl times/6.6 mm/sup 2/ containing a variety of types of these Test structures was implemented to demonstrate the design feasibility.

  • Addressable failure Site Test structures (AFS-TS) for process development and optimization
    ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095), 2000
    Co-Authors: K.y.-y. Doong, Sunnys Hsieh, Binson Shen, Wang Chien-jung, Yen-hen Ho, Jye-yen Cheng, Yeu-haw Yang, K. Miyamoto
    Abstract:

    Two types of addressable failure Site Test structures are developed. In-house program is coded to extract the electrical information and simulate the failure mode. A complete set of Test structure modules for 0.25 um logic backend of line process is implemented in a Test chip of 22/spl times/6.6 mm/sup 2/. By using the novel Test structure, the yield analysis and defect tracking of BEOL process development as well as low-k Fluorinated SiO/sub 2/ (FSG) process optimization are demonstrated.

  • Novel assessment of process control monitor in advanced semiconductor manufacturing: a complete set of addressable failure Site Test structures (AFS-TS)
    1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No.99CH36314), 1999
    Co-Authors: Sunnys Hsieh, K.y.-y. Doong, Jye-yen Cheng, Jian-rong Wang, Chia-wen Huang, Yu-hao Yang, K. Miyamoto
    Abstract:

    This work describes the implementation of a novel assessment of process control monitor in advanced semiconductor manufacturing. It manifests the design and simulation results of addressable failure Site Test structures. Four novel Test structures with three level interconnects have been developed and validated with an in-house simulation system. The novel Test structures are used to identify the locations of killer defects. A Test chip of 22/spl times/6.6 mm/sup 2/ containing four types Test structures was implemented using a 0.25 /spl mu/m logic backend of line process. This simple and efficient Test structure for killer defect identification demonstrated its superiority in yield enhancement.

  • Design and simulation of addressable failure Site Test structure for IC process control monitor
    1999 International Symposium on VLSI Technology Systems and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453), 1999
    Co-Authors: K.y.-y. Doong, Jye-yen Cheng
    Abstract:

    A novel Test structure to ensure failure addressable and high-density Test structure of semiconductor process control monitor with a limited number of contact pads required for electrical Test is described. The placement and routing scheme requires only two levels of conductive layers, and provides the maximum number of bridging and continuity Test structure units. A graph model is developed to manifest the spatial configuration of Test structure units and simplify the complexity of fault detection. Also, a generic algorithm of multi-fault detection was developed.