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Israel Koren - One of the best experts on this subject based on the ideXlab platform.

  • defect tolerance in vlsi circuits techniques and Yield Analysis
    Proceedings of the IEEE, 1998
    Co-Authors: Israel Koren, Zahava Koren
    Abstract:

    Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in Yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of Yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage Yield-enhancement techniques are aimed at making the integrated circuit "defect tolerant", i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate Yield projections. This paper reviews the currently used statistical Yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various Yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.

  • Yield Analysis of a novel scheme for defect-tolerant memories
    1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon, 1996
    Co-Authors: Israel Koren, Zahava Koren
    Abstract:

    The recent increases in the size of memory ICs have made designers realize that there exists a need for new defect-tolerance techniques, since the traditional methods are no longer effective. One such new technique, the Flexible Multi-Macro (FMM) technique has recently been suggested and implemented in a 1 Gb DRAM circuit. In this paper we present a Yield Analysis of the FMM design and compare its Yield to that of the most common defect-tolerance technique of adding spare rows and columns to the memory array.

  • a unified negative binomial distribution for Yield Analysis of defect tolerant circuits
    IEEE Transactions on Computers, 1993
    Co-Authors: Israel Koren, Zahava Koren, C H Stepper
    Abstract:

    It has been recognized that the Yield of fault-tolerant VLSI circuits depends on the size of the fault clusters. Consequently, models for Yield Analysis have been proposed for large-area clustering and small-area clustering, based on the two-parameter negative-binomial distribution. The addition of a new parameter, the block size, to the two existing parameters of the fault distribution is proposed. This parameter allows the unification of the existing models and, at the same time, adds a whole range of medium-size clustering models. Thus, the flexibility in choosing the appropriate Yield model is increased. Methods for estimating the newly defined block size are presented and the approach is validated through simulation and empirical data. >

  • A Unified Approach to Yield Analysis of Defect Tolerant Circuits
    Defect and Fault Tolerance in VLSI Systems, 1990
    Co-Authors: Zahava Koren, Israel Koren
    Abstract:

    The dependence of the Yield of defect tolerant VLSI circuits on the size of defect clusters (relative to the chip size) has been recently recognized. Consequently, models for Yield Analysis have been proposed for “large area clustering” and “small area clustering”. By adding a new parameter, the block size, to the existing parameters of the defect distribution we unify the Analysis of the existing models and at the same time add a whole range of “medium size clustering” models, thus increasing the flexibility in choosing the appropriate Yield model. We illustrate our approach through several numerical examples and propose methods for estimating the newly defined block size.

Zahava Koren - One of the best experts on this subject based on the ideXlab platform.

  • defect tolerance in vlsi circuits techniques and Yield Analysis
    Proceedings of the IEEE, 1998
    Co-Authors: Israel Koren, Zahava Koren
    Abstract:

    Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in Yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of Yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage Yield-enhancement techniques are aimed at making the integrated circuit "defect tolerant", i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate Yield projections. This paper reviews the currently used statistical Yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various Yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.

  • Yield Analysis of a novel scheme for defect-tolerant memories
    1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon, 1996
    Co-Authors: Israel Koren, Zahava Koren
    Abstract:

    The recent increases in the size of memory ICs have made designers realize that there exists a need for new defect-tolerance techniques, since the traditional methods are no longer effective. One such new technique, the Flexible Multi-Macro (FMM) technique has recently been suggested and implemented in a 1 Gb DRAM circuit. In this paper we present a Yield Analysis of the FMM design and compare its Yield to that of the most common defect-tolerance technique of adding spare rows and columns to the memory array.

  • a unified negative binomial distribution for Yield Analysis of defect tolerant circuits
    IEEE Transactions on Computers, 1993
    Co-Authors: Israel Koren, Zahava Koren, C H Stepper
    Abstract:

    It has been recognized that the Yield of fault-tolerant VLSI circuits depends on the size of the fault clusters. Consequently, models for Yield Analysis have been proposed for large-area clustering and small-area clustering, based on the two-parameter negative-binomial distribution. The addition of a new parameter, the block size, to the two existing parameters of the fault distribution is proposed. This parameter allows the unification of the existing models and, at the same time, adds a whole range of medium-size clustering models. Thus, the flexibility in choosing the appropriate Yield model is increased. Methods for estimating the newly defined block size are presented and the approach is validated through simulation and empirical data. >

  • A Unified Approach to Yield Analysis of Defect Tolerant Circuits
    Defect and Fault Tolerance in VLSI Systems, 1990
    Co-Authors: Zahava Koren, Israel Koren
    Abstract:

    The dependence of the Yield of defect tolerant VLSI circuits on the size of defect clusters (relative to the chip size) has been recently recognized. Consequently, models for Yield Analysis have been proposed for “large area clustering” and “small area clustering”. By adding a new parameter, the block size, to the existing parameters of the defect distribution we unify the Analysis of the existing models and at the same time add a whole range of “medium size clustering” models, thus increasing the flexibility in choosing the appropriate Yield model. We illustrate our approach through several numerical examples and propose methods for estimating the newly defined block size.

Wen-ben Jone - One of the best experts on this subject based on the ideXlab platform.

  • Yield Analysis for self-repairable MEMS devices
    Analog Integrated Circuits and Signal Processing, 2008
    Co-Authors: Xingguo Xiong, Yu-liang Wu, Wen-ben Jone
    Abstract:

    In this paper, Yield Analysis for a self-repairable MEMS (SRMEMS) accelerometer design is proposed. The accelerometer consists of (n + m) identical modules: n of them serve as the main device, while the remaining m modules act as the redundancy. The Yield model for MEMS redundancy repair is developed by statistical Analysis. Based upon the Yield model, the Yield increase after redundancy repair for different m and n numbers is analyzed. ANSYS Monte Carlo simulation is used to estimate the Yield of BISR/non-BISR MEMS devices with random point-stiction defects. The simulation results are in good agreement with the theoretical prediction based on our Yield model. The simulation results also show that the SRMEMS leads to effective Yield increase compared to non-BISRS design, especially for a moderate initial Yield.

  • Yield Analysis for self-repairable MEMS devices
    48th Midwest Symposium on Circuits and Systems 2005., 2005
    Co-Authors: Xingguo Xiong, Yu-liang Wu, Wen-ben Jone
    Abstract:

    In this paper, the Yield Analysis for a self-repairable MEMS (SRMEMS) accelerometer design is proposed. The accelerometer consists of (n + m) identical modules: n of them serve as the main device, while the remaining m modules act as the redundancy. The Yield model for MEMS redundancy repair is developed by statistical Analysis. Based upon the Yield model, the Yield increase after redundancy repair for the SRMEMS accelerometer is derived. The Yield increase versus initial Yield for different m numbers is simulated. The simulation results show that the SRMEMS leads to effective Yield increase compared to non-BISRS design, especially for a moderate initial Yield

Yan Wang - One of the best experts on this subject based on the ideXlab platform.

  • An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling
    IEEE Transactions on Very Large Scale Integration Systems, 2015
    Co-Authors: Zuochang Ye, Yan Wang
    Abstract:

    SRAM cells usually require extremely low failure rate or equivalently extremely high production Yield, making it impractical to perform Yield Analysis using Monte Carlo (MC) method as huge amount of samples are needed. Fast MC methods, e.g., importance sampling methods, are still too expensive as the anticipated failure rate is very low. In this paper, a new SRAM Yield Analysis method is proposed to tackle this issue. The key idea is to improve traditional importance sampling method with an efficient online surrogate model. Experimental results show that the proposed Yield Analysis method achieves $5\times $ – $22\times $ speedup over existing state-of-the-art techniques without sacrificing estimation accuracy. Sigma distribution and schmoo plot can be quickly generated by the proposed method, which is very useful for realistic applications. Based on the proposed Yield Analysis method, an efficient Yield optimization method has been developed to further automate the SRAM cell design procedure where process variations can be fully considered. Experimental results show that a fully automatic Yield optimization for SRAM cells can be done within only a few hours.

  • DATE - Efficient high-sigma Yield Analysis for high dimensional problems
    Design Automation & Test in Europe Conference & Exhibition (DATE) 2014, 2014
    Co-Authors: Moning Zhang, Zuochang Ye, Yan Wang
    Abstract:

    High-sigma Analysis is important for estimating the probability of rare events. Traditional high-sigma Analysis can only work for small-size (low-dimension) problems limiting to 10 ~ 20 random variables, mostly due to the difficulty of finding optimal boundary points. In this paper we propose an efficient method to deal with high-dimension problems. The proposed method is based on performing optimization in a series of low dimension parameter spaces. The final solution can be regarded as a greedy version of the global optimization. Experiments show that the proposed method can efficiently work with problems with > 100 independent variables.

  • Importance Boundary Sampling for SRAM Yield Analysis With Multiple Failure Regions
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014
    Co-Authors: Zuochang Ye, Yan Wang
    Abstract:

    SRAM cells generally require an extremely low failure rate (i.e., high Yield) in the per cell basis to ensure a reasonably moderate Yield for the whole chip. Existing Yield Analysis methods still encounter issues related to multiple failure regions resulting from high-dimensional process parameter space and/or multiple performance specifications. This paper proposes a new method that combines the advantages of existing importance sampling and boundary searching methods, and avoids issues in both. The key idea is to first find all likely failure regions and then, do importance sampling on these regions. Surrogate models are used to further accelerate the method so that SPICE-simulations can be highly reduced. Experimental results show that the proposed method is suitable for handling problems with multiple failure regions. Meanwhile, it can provide 5X ~ 20X speed-up over other existing techniques.

  • DATE - Efficient importance sampling for high-sigma Yield Analysis with adaptive online surrogate modeling
    Design Automation & Test in Europe Conference & Exhibition (DATE) 2013, 2013
    Co-Authors: Zuochang Ye, Yan Wang
    Abstract:

    Massively repeated structures such as SRAM cells usually require extremely low failure rate. This brings on a challenging issue for Monte Carlo based statistical Yield Analysis, as huge amount of samples have to be drawn in order to observe one single failure. Fast Monte Carlo methods, e.g. importance sampling methods, are still quite expensive as the anticipated failure rate is very low. In this paper, a new method is proposed to tackle this issue. The key idea is to improve traditional importance sampling method with an efficient online surrogate model. The proposed method improves the performance for both stages in importance sampling, i.e. finding the distorted probability density function, and the distorted sampling. Experimental results show that the proposed method is 1e2X~1e5X faster than the standard Monte Carlo approach and achieves 5X~22X speedup over existing state-of-the-art techniques without sacrificing estimation accuracy.

Xingguo Xiong - One of the best experts on this subject based on the ideXlab platform.

  • Yield Analysis for self-repairable MEMS devices
    Analog Integrated Circuits and Signal Processing, 2008
    Co-Authors: Xingguo Xiong, Yu-liang Wu, Wen-ben Jone
    Abstract:

    In this paper, Yield Analysis for a self-repairable MEMS (SRMEMS) accelerometer design is proposed. The accelerometer consists of (n + m) identical modules: n of them serve as the main device, while the remaining m modules act as the redundancy. The Yield model for MEMS redundancy repair is developed by statistical Analysis. Based upon the Yield model, the Yield increase after redundancy repair for different m and n numbers is analyzed. ANSYS Monte Carlo simulation is used to estimate the Yield of BISR/non-BISR MEMS devices with random point-stiction defects. The simulation results are in good agreement with the theoretical prediction based on our Yield model. The simulation results also show that the SRMEMS leads to effective Yield increase compared to non-BISRS design, especially for a moderate initial Yield.

  • Yield Analysis for self-repairable MEMS devices
    48th Midwest Symposium on Circuits and Systems 2005., 2005
    Co-Authors: Xingguo Xiong, Yu-liang Wu, Wen-ben Jone
    Abstract:

    In this paper, the Yield Analysis for a self-repairable MEMS (SRMEMS) accelerometer design is proposed. The accelerometer consists of (n + m) identical modules: n of them serve as the main device, while the remaining m modules act as the redundancy. The Yield model for MEMS redundancy repair is developed by statistical Analysis. Based upon the Yield model, the Yield increase after redundancy repair for the SRMEMS accelerometer is derived. The Yield increase versus initial Yield for different m numbers is simulated. The simulation results show that the SRMEMS leads to effective Yield increase compared to non-BISRS design, especially for a moderate initial Yield