The Experts below are selected from a list of 147 Experts worldwide ranked by ideXlab platform

Yuan Dong - One of the best experts on this subject based on the ideXlab platform.

  • Scalable Hierarchical Parallel Algorithm for the Solution of Super Large-Scale Sparse Linear Equations
    2014
    Co-Authors: Bin Liu, Yuan Dong
    Abstract:

    The parallel linear equations solver capable of effectively using 1000þ Processors becomes the bottleneck of large-scale implicit engineering simulations. In this paper, we present a new hierarchical parallel master-Slave-structural iterative algorithm for the solution of super large-scale sparse linear equations in a distributed memory computer cluster. Through alternatively performing global equilibrium computation and local relaxation, the specific accuracy requirement can be met in a few iterations. Moreover, each set/Slave-Processor majorly communicates with its nearest neighbors, and the transferring data between sets/Slave-Processors and the master-Processor is always far below the communi-cation between neighboring sets/Slave-Processors. The corresponding algorithm for implicit finite element analysis has been implemented based on the MPI library, and a super large 2-dimension square system of triangle-lattice truss structure under randomly distributed loadings is simulated with over 1 109 degrees of freedom (DOF) on up to 2001 Processors of the “Exploration 100 ” cluster in Tsinghua University. The numerical experiments dem-onstrate that this algorithm has excellent parallel efficiency and high scalability, and it may have broad applications in other implicit simulations. [DOI: 10.1115/1.4023481

  • Scalable hierarchical parallel algorithm for the solution of super large-scale sparse linear equations
    Journal of Applied Mechanics, 2013
    Co-Authors: Bin Liu, Yuan Dong
    Abstract:

    The parallel linear equations solver capable of effectively using 1000+ Processors becomes the bottleneck of large-scale implicit engineering simulations. In this paper, we present a new hierarchical parallel master-Slave-structural iterative algorithm for the solution of super large-scale sparse linear equations in distributed memory computer cluster. Through alternatively performing global equilibrium computation and local relaxation, our proposed algorithm will reach the specific accuracy requirement in a few of iterative steps. Moreover, each set/Slave-Processor majorly communicate with its nearest neighbors, and the transferring data between sets/Slave-Processors and master is always far below the set-neighbor communication. The corresponding algorithm for implicit finite element analysis has been implemented based on MPI library, and a super large 2-dimension square system of triangle-lattice truss structure under random static loads is simulated with over one billion degrees of freedom and up to 2001 Processors on "Exploration 100" cluster in Tsinghua University. The numerical experiments demonstrate that this algorithm has excellent parallel efficiency and high scalability, and it may have broad application in other implicit simulations.

Bin Liu - One of the best experts on this subject based on the ideXlab platform.

  • Scalable Hierarchical Parallel Algorithm for the Solution of Super Large-Scale Sparse Linear Equations
    2014
    Co-Authors: Bin Liu, Yuan Dong
    Abstract:

    The parallel linear equations solver capable of effectively using 1000þ Processors becomes the bottleneck of large-scale implicit engineering simulations. In this paper, we present a new hierarchical parallel master-Slave-structural iterative algorithm for the solution of super large-scale sparse linear equations in a distributed memory computer cluster. Through alternatively performing global equilibrium computation and local relaxation, the specific accuracy requirement can be met in a few iterations. Moreover, each set/Slave-Processor majorly communicates with its nearest neighbors, and the transferring data between sets/Slave-Processors and the master-Processor is always far below the communi-cation between neighboring sets/Slave-Processors. The corresponding algorithm for implicit finite element analysis has been implemented based on the MPI library, and a super large 2-dimension square system of triangle-lattice truss structure under randomly distributed loadings is simulated with over 1 109 degrees of freedom (DOF) on up to 2001 Processors of the “Exploration 100 ” cluster in Tsinghua University. The numerical experiments dem-onstrate that this algorithm has excellent parallel efficiency and high scalability, and it may have broad applications in other implicit simulations. [DOI: 10.1115/1.4023481

  • Scalable hierarchical parallel algorithm for the solution of super large-scale sparse linear equations
    Journal of Applied Mechanics, 2013
    Co-Authors: Bin Liu, Yuan Dong
    Abstract:

    The parallel linear equations solver capable of effectively using 1000+ Processors becomes the bottleneck of large-scale implicit engineering simulations. In this paper, we present a new hierarchical parallel master-Slave-structural iterative algorithm for the solution of super large-scale sparse linear equations in distributed memory computer cluster. Through alternatively performing global equilibrium computation and local relaxation, our proposed algorithm will reach the specific accuracy requirement in a few of iterative steps. Moreover, each set/Slave-Processor majorly communicate with its nearest neighbors, and the transferring data between sets/Slave-Processors and master is always far below the set-neighbor communication. The corresponding algorithm for implicit finite element analysis has been implemented based on MPI library, and a super large 2-dimension square system of triangle-lattice truss structure under random static loads is simulated with over one billion degrees of freedom and up to 2001 Processors on "Exploration 100" cluster in Tsinghua University. The numerical experiments demonstrate that this algorithm has excellent parallel efficiency and high scalability, and it may have broad application in other implicit simulations.

Xu Lun-hui - One of the best experts on this subject based on the ideXlab platform.

  • A Millimeter Wave Automotive Anti-collusion Radar System Based on DSP
    Microcomputer Information, 2008
    Co-Authors: Xu Lun-hui
    Abstract:

    The automotive radar is one of the methods of reducing traffic accident.In this paper the technology about automotive collision avoidance is discussed,and the principle of millimeter wave radar based on FMCW is described .A new design with master – Slave Processor based on DSP is presented and processing flow of software system are introduced,The radar can detects the roadblock in front of it immediately and gives an alarm signal when the parameters exceed the set value,and the traffic crash rate is reduced.

  • Application of DSP in Millimeter Wave Automotive Anti-Collusion Radar
    Ordnance Industry Automation, 2007
    Co-Authors: Xu Lun-hui
    Abstract:

    A new design with master-Slave Processor is adopted in the system of millimeter wave automotive anti-collusion radar based on DSP. The Slave Processor AT89C51 realizes man-machine interactive function, display and alarming control. The sound and light alarming unit is controlled by AT89C51 when the distance obtained by master Processor DSP exceeds the threshold. The signal in time domain is transformed into frequency domain through fast Fourier transform (FFT), and the result can be obtained from sampling.

Liu Pei-ji - One of the best experts on this subject based on the ideXlab platform.

  • Dual-Port RAM's Usage in the Research of the Flash Real-Time Storage
    Journal of Qingdao University, 2008
    Co-Authors: Liu Pei-ji
    Abstract:

    As the data writing operation of the NAND flash is based on the page programming, the former sampling frequency is limited on a low level. This paper offers a solution using the dual-Processor system with the structure of the dual-port RAM. The master Processor finishes the A/D convertion and buffers the result data on it's RAM until 200 Bytes before it is writen into the dual-port RAM. When the data reached the flash's one page, the Slave Processor reads the data and sends it into the flash by page programming.The research resloves the dual-port RAM's port competition problem and realizes the resource sharing between the master and the Slave Processor. Although in the higher sampling frequency, the acquired data can definitely be written into the flash in time.

  • Portable ECG Holter's Design Based on Dual-port RAM
    Chinese Medical Equipment Journal, 2008
    Co-Authors: Liu Pei-ji
    Abstract:

    Objective To transmit ECG signals through a portable dual-mcu ECG holter based dual-port RAM.Methods Dual-port RAM had two independent address,data and control buses,which allowed the two Processors accessed it's resource independently at different time.The master Processor buffered the acquired data on its RAM until the data accumulated to 200 Bytes.Then the 200 Bytes would be transferred into the dual-port RAM at one time.The Slave Processor was informed to fetch the data when it reached the flash's one whole page.Results Problems in such aspects were conquered as the port contention of dual-port RAM,limiting sampling frequency,data sharing between the master and Slave Processors as well as acquiring signals by the cache.Conclusion The portable dual-mcu ECG holter based dual-port RAM can be applied to transmission of ECG signals.

Richard L. Baker - One of the best experts on this subject based on the ideXlab platform.

  • An integrated circuit design for pruned tree-search vector quantization encoding with an off-chip controller
    IEEE Transactions on Circuits and Systems for Video Technology, 1992
    Co-Authors: R. Jain, A. Madisetti, Richard L. Baker
    Abstract:

    The design of an encoder for pruned tree-search vector quantization (VQ) is discussed. This allows near-optimal performance in a mean square error sense while keeping the hardware complexity low. The encoder is partitioned into a Slave Processor chip that computes the distance and performs minimizations and an off-chip controller that directs the search. Pointer addressing is exploited in the codebook memory to keep the controller hardware simple. Inputs to the Slave Processor include the source vectors, the code vectors; and external control signals. The Slave Processor outputs the index of the code vector that best approximates the input in a mean square error sense. The layout for the Slave Processor has been generated using a 1.2- mu m CMOS library and measures 5.76*6.6 mm/sup 2/. Critical path simulation with SPICE indicates a throughput of 89 million multiply-accumulates per second. This implies that real-time processing at MPEG rates can be achieved if the number of levels (N7) and the number of children at any node (M) obey the constraint M*N >