The Experts below are selected from a list of 11055 Experts worldwide ranked by ideXlab platform

Vijay Raghunathan - One of the best experts on this subject based on the ideXlab platform.

  • Sleep-Mode Voltage Scaling: Enabling SRAM Data Retention at Ultra-Low Power in Embedded Microcontrollers
    ACM Transactions on Embedded Computing Systems, 2016
    Co-Authors: Hrishikesh Jayakumar, Arnab Raha, Vijay Raghunathan
    Abstract:

    In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle Mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low-power (Sleep) Mode when idle and preserving application state either by retaining the data in situ in Static Random Access Memory (SRAM) or by checkpointing it to F lash . However, both of these approaches have notable drawbacks. In situ data retention requires the SRAM to remain powered in Sleep Mode, while checkpointing to F lash involves significant energy and time overheads. This article proposes a new ultra-low-power Sleep Mode for microcontrollers that overcomes the limitations of both of these approaches. Our technique, H ypnos , is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10× lower) than the typical operating voltage of the microcontroller. H ypnos exploits this observation by performing extreme voltage scaling when the microcontroller is in Sleep Mode. We implement and evaluate H ypnos for the TI MSP430G2452 microcontroller and show that the Microcontroller (MCU) draws only 26nA in the proposed Sleep Mode, which is 4× lower than a baseline Sleep Mode that preserves SRAM contents. Further, to reduce the overheads associated with performing the voltage scaling, we propose the use of an energy harvesting source for providing the scaled supply voltage and demonstrate (using a light sensing photodiode) that the current consumption in the proposed Sleep Mode can be reduced to 1nA, which is 100× lower than the current consumption in the baseline low-power Mode. We also show that the decrease in Sleep-Mode power consumption translates to a reduction in application-level energy consumption by as much as 6.45×. By decreasing the average power consumption to such minuscule levels, H ypnos takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.

  • hypnos an ultra low power Sleep Mode with sram data retention for embedded microcontrollers
    International Conference on Hardware Software Codesign and System Synthesis, 2014
    Co-Authors: Hrishikesh Jayakumar, Arnab Raha, Vijay Raghunathan
    Abstract:

    In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle Mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low power (Sleep) state when idle, and preserving application state either by retaining the data in-situ in SRAM, or by checkpointing it to Flash. However, both these approaches have notable drawbacks. In-situ data retention requires the SRAM to remain powered in Sleep Mode, while checkpointing to Flash involves significant energy and time overheads. This paper proposes a new ultra-low power Sleep Mode for microcontrollers that overcomes the limitations of both these approaches. Our technique, Hypnos, is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10x lower) than the typical operating voltage of the microcontroller. Hypnos exploits this observation by performing extreme voltage scaling when the microcontroller is in Sleep Mode. We implement and evaluate Hypnos for the TI MSP430G2452 microcontroller and show that the MCU draws only 26nA in the proposed Sleep Mode, which is 4x lower than any existing Sleep Mode that preserves SRAM contents. Further, we show that a complete wireless sensing system using Hypnos only depletes battery capacity by 42.6nAh in an hour. By decreasing the average power consumption to such minuscule levels, Hypnos takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.

Sang-soo Lee - One of the best experts on this subject based on the ideXlab platform.

  • Energy-efficient PON with Sleep-Mode ONU: progress, challenges, and solutions
    IEEE Network, 2012
    Co-Authors: Lei Shi, Biswanath Mukherjee, Sang-soo Lee
    Abstract:

    Energy usage in our networks is increasing rapidly; and to conserve energy, progress has been made in designing energy-efficient passive optical networks, which are being widely deployed for broadband access. Among the various energy-saving techniques, enabling Sleep Mode in optical network units is a very promising approach. However, the slow transition of power from active Mode to Sleep Mode in an optical network unit, and the relatively large recovery and synchronization time needed during the wakeup process are challenges that need to be addressed. In this regard, we propose a service-level-agreement-based scheduling scheme for passive optical networks in which the optical line terminal can adjust the Sleep time and the optical network unit can quit Sleep Mode for sending high-priority packets. The trade-off in energy savings vs. delay performance is evaluated using simulations under practical power consumption settings.

  • ICTC - Power saved OLT and ONU with cyclic Sleep Mode operating in WDM-PON
    2012 International Conference on ICT Convergence (ICTC), 2012
    Co-Authors: Han Hyub Lee, Kwang-ok Kim, Jong Hyun Lee, Sang-soo Lee
    Abstract:

    We have proposed protocol based WDM-PON power saving mechanism with cyclic Sleep-Mode ONU and OLT for Green access network. Power saving Models show that the each home-gateway styled tunable ONU and OLT could reduce efficiently the power consumption around 70 % when the ratio of Sleep-Mode time and wakeup-Mode time set to 0.1.

  • Determination of Sleep Period for Cyclic Sleep Mode in XG-PON Power Management
    IEEE Communications Letters, 2012
    Co-Authors: Hakjeon Bang, Sang-soo Lee, Jongdeog Kim, Chang-soo Park
    Abstract:

    In 10-gigabit-capable passive optical network (XG-PON) power management, performance indexes such as power consumption and state transition delay of cyclic Sleep Mode are influenced by a Sleep period. In this letter, we determine the Sleep period to balance the performance tradeoff between these two conflicting goals. To do this, we perform a mathematical analysis using the state probability based on traffic arrivals. The effectiveness of the proposed Model is then confirmed by the numerical results of cyclic Sleep Mode.

Zhang Yan - One of the best experts on this subject based on the ideXlab platform.

  • Improved algorithm of IEEE 802.16j relay station Sleep Mode
    Computer Engineering and Applications, 2010
    Co-Authors: Zhang Yan
    Abstract:

    The IEEE 802.16j standard introduces Relay Station(RS)based on the IEEE 802.16e standard.RS Sleep Mode is essential for power saving.The parameters have great impact on the effect of RS Sleep Mode,namely average energy consumption and average frame delay.In this paper,the system Models for the energy consumption and the average frame delay affected by RS Sleep Mode are built using statistics.By analyzing the parameters,an improved algorithm that dynamically changing parameters based on traffic stream are proposed.The average energy consumption and average frame delay are analyzed by simulation results at last of the paper.

  • Improved Sleep Mode algorithm of IEEE802.16e
    Computer Engineering and Applications, 2009
    Co-Authors: Zhang Yan
    Abstract:

    The IEEE802.16e provides a technique called "Sleep Mode" to save the energy consumption of the MSS and a standard Sleep Mode control algorithm is given.This paper proposes an improved Sleep Mode control algorithm,which adjusts adaptively the Sleep Mode interval according to the traffic rate.Then this paper compares the 802.16e standard algorithm and the improved algorithm under four actual Models.It has been observed that the proposed algorithm for Sleep Mode saves substantial amount of energy at lower traffic and almost same at higher traffic as compared to 802.16e.

  • Improved Sleep Mode Algorithm of IEEE 802.16e
    Computer Engineering, 2009
    Co-Authors: Zhang Yan
    Abstract:

    The IEEE 802.16e standard adopts Sleep Mode to save the energy consumption of the mobile station.This paper proposes an improved Sleep Mode control algorithm,which dynamically adjusts the Sleep period of Sleep Mode according to the access speed.It compares the IEEE 802.16e standard algorithm and the improved algorithm under four actual Models,and the results show that the improved algorithm Mode saves substantial amount of energy at low access speed and has the same performance as the standard algorithm at high access speed.

  • An Adaptive Algorithm for Sleep Mode Based on IEEE 802.16e
    Journal of Electrical & Electronic Education, 2008
    Co-Authors: Zhang Yan
    Abstract:

    In order to minimize the MS power consumption and decrease the occupation of interface resources in BS,the Sleep Mode is introduced in the standard IEEE 802.16e.This paper analyses the power consumption and the delay of IEEE 802.16e Sleep Mode operation with a theoretical Markov chain Model.The analytical results show that there is a tradeoff between the power consumption and the delay,and the key of the tradeoff is the initial Sleep window.Then an adaptive algorithm to adjust the initial Sleep window dynamically according to the traffic load is presented.Simulation shows that the power of the proposed algorithm can save 20% compared to the IEEE 802.16e standard,the price is just little increase of the delay.

Hrishikesh Jayakumar - One of the best experts on this subject based on the ideXlab platform.

  • Sleep-Mode Voltage Scaling: Enabling SRAM Data Retention at Ultra-Low Power in Embedded Microcontrollers
    ACM Transactions on Embedded Computing Systems, 2016
    Co-Authors: Hrishikesh Jayakumar, Arnab Raha, Vijay Raghunathan
    Abstract:

    In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle Mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low-power (Sleep) Mode when idle and preserving application state either by retaining the data in situ in Static Random Access Memory (SRAM) or by checkpointing it to F lash . However, both of these approaches have notable drawbacks. In situ data retention requires the SRAM to remain powered in Sleep Mode, while checkpointing to F lash involves significant energy and time overheads. This article proposes a new ultra-low-power Sleep Mode for microcontrollers that overcomes the limitations of both of these approaches. Our technique, H ypnos , is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10× lower) than the typical operating voltage of the microcontroller. H ypnos exploits this observation by performing extreme voltage scaling when the microcontroller is in Sleep Mode. We implement and evaluate H ypnos for the TI MSP430G2452 microcontroller and show that the Microcontroller (MCU) draws only 26nA in the proposed Sleep Mode, which is 4× lower than a baseline Sleep Mode that preserves SRAM contents. Further, to reduce the overheads associated with performing the voltage scaling, we propose the use of an energy harvesting source for providing the scaled supply voltage and demonstrate (using a light sensing photodiode) that the current consumption in the proposed Sleep Mode can be reduced to 1nA, which is 100× lower than the current consumption in the baseline low-power Mode. We also show that the decrease in Sleep-Mode power consumption translates to a reduction in application-level energy consumption by as much as 6.45×. By decreasing the average power consumption to such minuscule levels, H ypnos takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.

  • hypnos an ultra low power Sleep Mode with sram data retention for embedded microcontrollers
    International Conference on Hardware Software Codesign and System Synthesis, 2014
    Co-Authors: Hrishikesh Jayakumar, Arnab Raha, Vijay Raghunathan
    Abstract:

    In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle Mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low power (Sleep) state when idle, and preserving application state either by retaining the data in-situ in SRAM, or by checkpointing it to Flash. However, both these approaches have notable drawbacks. In-situ data retention requires the SRAM to remain powered in Sleep Mode, while checkpointing to Flash involves significant energy and time overheads. This paper proposes a new ultra-low power Sleep Mode for microcontrollers that overcomes the limitations of both these approaches. Our technique, Hypnos, is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10x lower) than the typical operating voltage of the microcontroller. Hypnos exploits this observation by performing extreme voltage scaling when the microcontroller is in Sleep Mode. We implement and evaluate Hypnos for the TI MSP430G2452 microcontroller and show that the MCU draws only 26nA in the proposed Sleep Mode, which is 4x lower than any existing Sleep Mode that preserves SRAM contents. Further, we show that a complete wireless sensing system using Hypnos only depletes battery capacity by 42.6nAh in an hour. By decreasing the average power consumption to such minuscule levels, Hypnos takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.

Raisa O. C. Hirafuji - One of the best experts on this subject based on the ideXlab platform.

  • NaNA - Energy Efficiency Analysis of the Watchful Sleep Mode with Delayed Wakeup in PONs
    2018 International Conference on Networking and Network Applications (NaNA), 2018
    Co-Authors: Raisa O. C. Hirafuji, Divanilson R. Campelo, Ahmad R. Dhaini, Limei Peng
    Abstract:

    Over the last decade, passive optical network (PON) has been taken as the most promising next-generation access network. To improve the energy efficiency in PON systems, the ITU-T standard for next-generation PON system introduced a new power management Mode, so-called the Watchful Sleep Mode. This new Mode is expected to be operated on any TDM-PON or GPON variant. Although the Sleep mechanism under the Watchful Sleep Mode is well defined, its performance can vary greatly depending on the criteria used to start and/or terminate the power saving phase. In this article, we present a comprehensive analytical Model for evaluating the energy efficiency of the watchful Sleep Mode using the Delayed Wakeup (DWU) mechanism. We then compare its performance with the Immediate Wakeup (IWU) scheme. Our analytical and simulation results highlight the accuracy of the presented Model and prove its merits.

  • the watchful Sleep Mode a new standard for energy efficiency in future access networks
    IEEE Communications Magazine, 2015
    Co-Authors: Raisa O. C. Hirafuji, Divanilson R. Campelo, Ahmad R. Dhaini, Kelvin Cunha, Denis A Khotimsky
    Abstract:

    The continuously increasing consumption of power to access the Internet has been a major concern for network operators and equipment vendors. Passive optical network (PON) systems are widely seen as the future of broadband access. In 2010, ITU-T standardized a protocol-based PON energy efficiency mechanism that is comprised of two main Modes, the doze Mode and the cyclic Sleep Mode, which promise to save significant amounts of energy. However, the use of these two standardized alternative Modes requires extra signaling and wastes energy. In this article we present the watchful Sleep Mode, a new Mode that unifies the doze and cyclic Sleep Modes into a single power management Mode. The new Mode eliminates the extra control signaling and maximizes the amount of energy saved by keeping only the necessary hardware ON. Recently, the watchful Sleep Mode has been included in the ITU-T G.984 (G-PON) and ITUT G.987 (XG-PON) recommendations. It is expected to be operated as the only power management Mode in future PON systems.