The Experts below are selected from a list of 336 Experts worldwide ranked by ideXlab platform

Sotirios G. Ziavras - One of the best experts on this subject based on the ideXlab platform.

  • Novel FPGA-based signature matching for deep packet inspection
    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2010
    Co-Authors: Nitesh B. Guinde, Sotirios G. Ziavras
    Abstract:

    Deep packet inspection forms the backbone of any Network intrusion Detection (NID) system. It involves matching known malicious patterns against the incoming traffic payload. Pattern matching in software is prohibitively slow in comparison to current network speeds. Thus, only FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) solutions could be efficient for this problem. Our FPGA-based solution performs high-speed matching while permitting pattern updates without resource reconfiguration. An off-line optimization method first finds sub-pattern similarities across all the patterns in the Snort Database of signatures 17. A novel technique then compresses each pattern into a bit vector where each bit represents such a sub-pattern. Our approach reduces drastically the required on-chip storage as well as the complexity of matching, utilizing just 0.05 logic cells for processing and 17.74 bits for storage per character in the current Snort Database of 6456 patterns.

  • WISTP - Novel FPGA-Based signature matching for deep packet inspection
    Information Security Theory and Practices. Security and Privacy of Pervasive Systems and Smart Devices, 2010
    Co-Authors: Nitesh B. Guinde, Sotirios G. Ziavras
    Abstract:

    Deep packet inspection forms the backbone of any Network Intrusion Detection (NID) system. It involves matching known malicious patterns against the incoming traffic payload. Pattern matching in software is prohibitively slow in comparison to current network speeds. Thus, only FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) solutions could be efficient for this problem. Our FPGA-based solution performs high-speed matching while permitting pattern updates without resource reconfiguration. An off-line optimization method first finds sub-pattern similarities across all the patterns in the Snort Database of signatures [17]. A novel technique then compresses each pattern into a bit vector where each bit represents such a sub-pattern. Our approach reduces drastically the required on-chip storage as well as the complexity of matching, utilizing just 0.05 logic cells for processing and 17.74 bits for storage per character in the current Snort Database of 6456 patterns.

  • Efficient hardware support for pattern matching in network intrusion detection
    Computers & Security, 2010
    Co-Authors: Nitesh B. Guinde, Sotirios G. Ziavras
    Abstract:

    Deep packet inspection forms the backbone of any Network Intrusion Detection (NID) system. It involves matching known malicious patterns against the incoming traffic payload. Pattern matching in software is prohibitively slow in comparison to current network speeds. Due to the high complexity of matching, only FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) platforms can provide efficient solutions. FPGAs facilitate target architecture specialization due to their field programmability. Costly ASIC designs, on the other hand, are normally resilient to pattern updates. Our FPGA-based solution performs high-speed pattern matching while permitting pattern updates without resource reconfiguration. To its advantage, our solution can be adopted by software and ASIC realizations, however at the expense of much lower performance and higher price, respectively. Our solution permits the NID system to function while pattern updates occur. An off-line optimization method first finds common sub-patterns across all the patterns in the Snort Database of signatures. A novel technique then compresses each pattern into a bit vector, where each bit represents such a sub-pattern. This approach reduces drastically the required on-chip storage as well as the complexity of pattern matching. The bit vectors for newly discovered patterns can be generated easily using a simple high-level language program before storing them into the on-chip RAM. Compared to earlier approaches, not only is our strategy very efficient while supporting runtime updates but it also results in impressive area savings; it utilizes just 0.052 logic cells for processing and 17.77 bits for storage per character in the current Snort Database of 6455 patterns. Also, the total number of logic cells for processing the traffic payload does not change with pattern updates.

Nitesh B. Guinde - One of the best experts on this subject based on the ideXlab platform.

  • Novel FPGA-based signature matching for deep packet inspection
    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2010
    Co-Authors: Nitesh B. Guinde, Sotirios G. Ziavras
    Abstract:

    Deep packet inspection forms the backbone of any Network intrusion Detection (NID) system. It involves matching known malicious patterns against the incoming traffic payload. Pattern matching in software is prohibitively slow in comparison to current network speeds. Thus, only FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) solutions could be efficient for this problem. Our FPGA-based solution performs high-speed matching while permitting pattern updates without resource reconfiguration. An off-line optimization method first finds sub-pattern similarities across all the patterns in the Snort Database of signatures 17. A novel technique then compresses each pattern into a bit vector where each bit represents such a sub-pattern. Our approach reduces drastically the required on-chip storage as well as the complexity of matching, utilizing just 0.05 logic cells for processing and 17.74 bits for storage per character in the current Snort Database of 6456 patterns.

  • WISTP - Novel FPGA-Based signature matching for deep packet inspection
    Information Security Theory and Practices. Security and Privacy of Pervasive Systems and Smart Devices, 2010
    Co-Authors: Nitesh B. Guinde, Sotirios G. Ziavras
    Abstract:

    Deep packet inspection forms the backbone of any Network Intrusion Detection (NID) system. It involves matching known malicious patterns against the incoming traffic payload. Pattern matching in software is prohibitively slow in comparison to current network speeds. Thus, only FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) solutions could be efficient for this problem. Our FPGA-based solution performs high-speed matching while permitting pattern updates without resource reconfiguration. An off-line optimization method first finds sub-pattern similarities across all the patterns in the Snort Database of signatures [17]. A novel technique then compresses each pattern into a bit vector where each bit represents such a sub-pattern. Our approach reduces drastically the required on-chip storage as well as the complexity of matching, utilizing just 0.05 logic cells for processing and 17.74 bits for storage per character in the current Snort Database of 6456 patterns.

  • Efficient hardware support for pattern matching in network intrusion detection
    Computers & Security, 2010
    Co-Authors: Nitesh B. Guinde, Sotirios G. Ziavras
    Abstract:

    Deep packet inspection forms the backbone of any Network Intrusion Detection (NID) system. It involves matching known malicious patterns against the incoming traffic payload. Pattern matching in software is prohibitively slow in comparison to current network speeds. Due to the high complexity of matching, only FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) platforms can provide efficient solutions. FPGAs facilitate target architecture specialization due to their field programmability. Costly ASIC designs, on the other hand, are normally resilient to pattern updates. Our FPGA-based solution performs high-speed pattern matching while permitting pattern updates without resource reconfiguration. To its advantage, our solution can be adopted by software and ASIC realizations, however at the expense of much lower performance and higher price, respectively. Our solution permits the NID system to function while pattern updates occur. An off-line optimization method first finds common sub-patterns across all the patterns in the Snort Database of signatures. A novel technique then compresses each pattern into a bit vector, where each bit represents such a sub-pattern. This approach reduces drastically the required on-chip storage as well as the complexity of pattern matching. The bit vectors for newly discovered patterns can be generated easily using a simple high-level language program before storing them into the on-chip RAM. Compared to earlier approaches, not only is our strategy very efficient while supporting runtime updates but it also results in impressive area savings; it utilizes just 0.052 logic cells for processing and 17.77 bits for storage per character in the current Snort Database of 6455 patterns. Also, the total number of logic cells for processing the traffic payload does not change with pattern updates.

Srinivas Aluru - One of the best experts on this subject based on the ideXlab platform.

  • Evaluating High Performance Pattern Matching on the Automata Processor
    IEEE Transactions on Computers, 2019
    Co-Authors: Indranil Roy, Marziyeh Nourian, Michela Becchi, Ankit Srivastava, Matt Grimm, Srinivas Aluru
    Abstract:

    In this paper, we study the acceleration of applications that identify all the occurrences of thousands of string-patterns in an input data-stream using the Automata Processor (AP). For this evaluation, we use two applications from two fields, namely, cybersecurity and bioinformatics. The first application, called Fast-SNAP, scans network data for 4312 signatures of intrusion derived from the popular open-source Snort Database. Using the resources of a single AP-board, Fast-SNAP can scan for all these signatures at 1 Gbps. The second application, called PROTOMATA, looks for all the occurrences of 1,309 motifs from the PROSITE Database in protein sequences. PROTOMATA is up to 68 times faster than the state-of-the-art CPU implementation. As a comparison, we emulate the execution of the same NFAs by programming FPGAs using state-of-the-art techniques. We find that the performance derived by using the resources of a single AP-board, which houses 32 AP-chips, is comparable to that of the resources of five to six large FPGAs. The design techniques used in this paper are generic and may be applicable to the development of similar applications on the AP.

  • High Performance Pattern Matching Using the Automata Processor
    2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2016
    Co-Authors: Indranil Roy, Marziyeh Nourian, Michela Becchi, Ankit Srivastava, Srinivas Aluru
    Abstract:

    In this paper, we study the acceleration of applications that require searching for all occurrences of thousands of string-patterns in an input data-stream, using the Automata Processor (AP). For this purpose, we use two applications from two fields, namely, network security and bioinformatics. The first application, called Fast-SNAP (for Fast-Snort using AP), scans network data for 4312 signatures of intrusion derived from the popular open-source Snort Database. Using the resources of a single AP board, Fast-SNAP can scan for all these signatures at 10.3 Gbps. The second application, called PROTOMATA (for PROTein autOMATA), looks for all occurrences of 1308 protein motifs from the PROSITE Database in protein sequences. PROTOMATA is up to half a million times faster than its single-CPU-based counterpart. The techniques developed to program these applications may be useful in the design and development of similar applications using this new hardware accelerator.

  • IPDPS - High Performance Pattern Matching Using the Automata Processor
    2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2016
    Co-Authors: Indranil Roy, Marziyeh Nourian, Michela Becchi, Ankit Srivastava, Srinivas Aluru
    Abstract:

    In this paper, we study the acceleration of applications that require searching for all occurrences of thousands of string-patterns in an input data-stream, using the Automata Processor (AP). For this purpose, we use two applications from two fields, namely, network security and bioinformatics. The first application, called Fast-SNAP (for Fast-Snort using AP), scans network data for 4312 signatures of intrusion derived from the popular open-source Snort Database. Using the resources of a single AP board, Fast-SNAP can scan for all these signatures at 10.3 Gbps. The second application, called PROTOMATA (for PROTein autOMATA), looks for all occurrences of 1308 protein motifs from the PROSITE Database in protein sequences. PROTOMATA is up to half a million times faster than its single-CPU-based counterpart. The techniques developed to program these applications may be useful in the design and development of similar applications using this new hardware accelerator.

Indranil Roy - One of the best experts on this subject based on the ideXlab platform.

  • Evaluating High Performance Pattern Matching on the Automata Processor
    IEEE Transactions on Computers, 2019
    Co-Authors: Indranil Roy, Marziyeh Nourian, Michela Becchi, Ankit Srivastava, Matt Grimm, Srinivas Aluru
    Abstract:

    In this paper, we study the acceleration of applications that identify all the occurrences of thousands of string-patterns in an input data-stream using the Automata Processor (AP). For this evaluation, we use two applications from two fields, namely, cybersecurity and bioinformatics. The first application, called Fast-SNAP, scans network data for 4312 signatures of intrusion derived from the popular open-source Snort Database. Using the resources of a single AP-board, Fast-SNAP can scan for all these signatures at 1 Gbps. The second application, called PROTOMATA, looks for all the occurrences of 1,309 motifs from the PROSITE Database in protein sequences. PROTOMATA is up to 68 times faster than the state-of-the-art CPU implementation. As a comparison, we emulate the execution of the same NFAs by programming FPGAs using state-of-the-art techniques. We find that the performance derived by using the resources of a single AP-board, which houses 32 AP-chips, is comparable to that of the resources of five to six large FPGAs. The design techniques used in this paper are generic and may be applicable to the development of similar applications on the AP.

  • High Performance Pattern Matching Using the Automata Processor
    2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2016
    Co-Authors: Indranil Roy, Marziyeh Nourian, Michela Becchi, Ankit Srivastava, Srinivas Aluru
    Abstract:

    In this paper, we study the acceleration of applications that require searching for all occurrences of thousands of string-patterns in an input data-stream, using the Automata Processor (AP). For this purpose, we use two applications from two fields, namely, network security and bioinformatics. The first application, called Fast-SNAP (for Fast-Snort using AP), scans network data for 4312 signatures of intrusion derived from the popular open-source Snort Database. Using the resources of a single AP board, Fast-SNAP can scan for all these signatures at 10.3 Gbps. The second application, called PROTOMATA (for PROTein autOMATA), looks for all occurrences of 1308 protein motifs from the PROSITE Database in protein sequences. PROTOMATA is up to half a million times faster than its single-CPU-based counterpart. The techniques developed to program these applications may be useful in the design and development of similar applications using this new hardware accelerator.

  • IPDPS - High Performance Pattern Matching Using the Automata Processor
    2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2016
    Co-Authors: Indranil Roy, Marziyeh Nourian, Michela Becchi, Ankit Srivastava, Srinivas Aluru
    Abstract:

    In this paper, we study the acceleration of applications that require searching for all occurrences of thousands of string-patterns in an input data-stream, using the Automata Processor (AP). For this purpose, we use two applications from two fields, namely, network security and bioinformatics. The first application, called Fast-SNAP (for Fast-Snort using AP), scans network data for 4312 signatures of intrusion derived from the popular open-source Snort Database. Using the resources of a single AP board, Fast-SNAP can scan for all these signatures at 10.3 Gbps. The second application, called PROTOMATA (for PROTein autOMATA), looks for all occurrences of 1308 protein motifs from the PROSITE Database in protein sequences. PROTOMATA is up to half a million times faster than its single-CPU-based counterpart. The techniques developed to program these applications may be useful in the design and development of similar applications using this new hardware accelerator.

Marziyeh Nourian - One of the best experts on this subject based on the ideXlab platform.

  • Evaluating High Performance Pattern Matching on the Automata Processor
    IEEE Transactions on Computers, 2019
    Co-Authors: Indranil Roy, Marziyeh Nourian, Michela Becchi, Ankit Srivastava, Matt Grimm, Srinivas Aluru
    Abstract:

    In this paper, we study the acceleration of applications that identify all the occurrences of thousands of string-patterns in an input data-stream using the Automata Processor (AP). For this evaluation, we use two applications from two fields, namely, cybersecurity and bioinformatics. The first application, called Fast-SNAP, scans network data for 4312 signatures of intrusion derived from the popular open-source Snort Database. Using the resources of a single AP-board, Fast-SNAP can scan for all these signatures at 1 Gbps. The second application, called PROTOMATA, looks for all the occurrences of 1,309 motifs from the PROSITE Database in protein sequences. PROTOMATA is up to 68 times faster than the state-of-the-art CPU implementation. As a comparison, we emulate the execution of the same NFAs by programming FPGAs using state-of-the-art techniques. We find that the performance derived by using the resources of a single AP-board, which houses 32 AP-chips, is comparable to that of the resources of five to six large FPGAs. The design techniques used in this paper are generic and may be applicable to the development of similar applications on the AP.

  • High Performance Pattern Matching Using the Automata Processor
    2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2016
    Co-Authors: Indranil Roy, Marziyeh Nourian, Michela Becchi, Ankit Srivastava, Srinivas Aluru
    Abstract:

    In this paper, we study the acceleration of applications that require searching for all occurrences of thousands of string-patterns in an input data-stream, using the Automata Processor (AP). For this purpose, we use two applications from two fields, namely, network security and bioinformatics. The first application, called Fast-SNAP (for Fast-Snort using AP), scans network data for 4312 signatures of intrusion derived from the popular open-source Snort Database. Using the resources of a single AP board, Fast-SNAP can scan for all these signatures at 10.3 Gbps. The second application, called PROTOMATA (for PROTein autOMATA), looks for all occurrences of 1308 protein motifs from the PROSITE Database in protein sequences. PROTOMATA is up to half a million times faster than its single-CPU-based counterpart. The techniques developed to program these applications may be useful in the design and development of similar applications using this new hardware accelerator.

  • IPDPS - High Performance Pattern Matching Using the Automata Processor
    2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2016
    Co-Authors: Indranil Roy, Marziyeh Nourian, Michela Becchi, Ankit Srivastava, Srinivas Aluru
    Abstract:

    In this paper, we study the acceleration of applications that require searching for all occurrences of thousands of string-patterns in an input data-stream, using the Automata Processor (AP). For this purpose, we use two applications from two fields, namely, network security and bioinformatics. The first application, called Fast-SNAP (for Fast-Snort using AP), scans network data for 4312 signatures of intrusion derived from the popular open-source Snort Database. Using the resources of a single AP board, Fast-SNAP can scan for all these signatures at 10.3 Gbps. The second application, called PROTOMATA (for PROTein autOMATA), looks for all occurrences of 1308 protein motifs from the PROSITE Database in protein sequences. PROTOMATA is up to half a million times faster than its single-CPU-based counterpart. The techniques developed to program these applications may be useful in the design and development of similar applications using this new hardware accelerator.