The Experts below are selected from a list of 15585 Experts worldwide ranked by ideXlab platform
B. Narahari - One of the best experts on this subject based on the ideXlab platform.
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flexible Software protection using hardware Software Codesign techniques
Design Automation and Test in Europe, 2004Co-Authors: J. Zambreno, A. Choudhary, R. Simha, B. NarahariAbstract:A strong level of trust in the Software running on an embedded processor is a prerequisite for its widespread deployment in any high-risk system. The expanding field of Software protection attempts to address the key steps used by hackers in attacking a Software system. In this paper we present an efficient and tunable approach to some problems in embedded Software protection that utilizes a hardware/Software Codesign methodology. By coupling our protective compiler techniques with reconfigurable hardware support, we allow for a greater flexibility of placement on the security-performance spectrum than previously proposed mainly-hardware or Software approaches. Results show that for most of our benchmarks, the average performance penalty of our approach is less than 20%, and that this number can be greatly improved upon with the proper utilization of compiler and architectural optimizations.
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Flexible Software protection using hardware/Software Codesign techniques
Proceedings Design Automation and Test in Europe Conference and Exhibition, 2004Co-Authors: J. Zambreno, A. Choudhary, R. Simha, B. NarahariAbstract:A strong level of trust in the Software running on an embedded processor is a prerequisite for its widespread deployment in any high-risk system. The expanding field of Software protection attempts to address the key steps used by hackers in attacking a Software system. In this paper we present an efficient and tunable approach to some problems in embedded Software protection that utilizes a hardware/Software Codesign methodology. By coupling our protective compiler techniques with reconfigurable hardware support, we allow for a greater flexibility of placement on the security-performance spectrum than previously proposed mainly-hardware or Software approaches. Results show that for most of our benchmarks, the average performance penalty of our approach is less than 20%, and that this number can be greatly improved upon with the proper utilization of compiler and architectural optimizations.
J. Zambreno - One of the best experts on this subject based on the ideXlab platform.
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flexible Software protection using hardware Software Codesign techniques
Design Automation and Test in Europe, 2004Co-Authors: J. Zambreno, A. Choudhary, R. Simha, B. NarahariAbstract:A strong level of trust in the Software running on an embedded processor is a prerequisite for its widespread deployment in any high-risk system. The expanding field of Software protection attempts to address the key steps used by hackers in attacking a Software system. In this paper we present an efficient and tunable approach to some problems in embedded Software protection that utilizes a hardware/Software Codesign methodology. By coupling our protective compiler techniques with reconfigurable hardware support, we allow for a greater flexibility of placement on the security-performance spectrum than previously proposed mainly-hardware or Software approaches. Results show that for most of our benchmarks, the average performance penalty of our approach is less than 20%, and that this number can be greatly improved upon with the proper utilization of compiler and architectural optimizations.
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Flexible Software protection using hardware/Software Codesign techniques
Proceedings Design Automation and Test in Europe Conference and Exhibition, 2004Co-Authors: J. Zambreno, A. Choudhary, R. Simha, B. NarahariAbstract:A strong level of trust in the Software running on an embedded processor is a prerequisite for its widespread deployment in any high-risk system. The expanding field of Software protection attempts to address the key steps used by hackers in attacking a Software system. In this paper we present an efficient and tunable approach to some problems in embedded Software protection that utilizes a hardware/Software Codesign methodology. By coupling our protective compiler techniques with reconfigurable hardware support, we allow for a greater flexibility of placement on the security-performance spectrum than previously proposed mainly-hardware or Software approaches. Results show that for most of our benchmarks, the average performance penalty of our approach is less than 20%, and that this number can be greatly improved upon with the proper utilization of compiler and architectural optimizations.
Kurt Keutzer - One of the best experts on this subject based on the ideXlab platform.
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INTERSPEECH - Hardware/Software Codesign for mobile speech recognition.
2020Co-Authors: David Sheffield, Michael J Anderson, Kurt KeutzerAbstract:In this paper, we explore high performance Software and hardware implementations of an automatic speech recognition system that can run locally on a mobile device. We automate the generation of key components of our speech recognition system using Three Fingered Jack, a tool for hardware/Software Codesign that maps computation to CPUs, data parallel processors, and custom hardware. We use Three Fingered Jack to explore energy and performance for two key kernels in our speech recognizer, the observation probability evaluation and across-word traversal. Through detailed hardware simulation and measurement, we produce accurate estimates for energy and area and show a significant energy improvement over a conventional mobile CPU.
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hardware Software Codesign for mobile speech recognition
Conference of the International Speech Communication Association, 2013Co-Authors: David Sheffield, Michael J Anderson, Kurt KeutzerAbstract:In this paper, we explore high performance Software and hardware implementations of an automatic speech recognition system that can run locally on a mobile device. We automate the generation of key components of our speech recognition system using Three Fingered Jack, a tool for hardware/Software Codesign that maps computation to CPUs, data parallel processors, and custom hardware. We use Three Fingered Jack to explore energy and performance for two key kernels in our speech recognizer, the observation probability evaluation and across-word traversal. Through detailed hardware simulation and measurement, we produce accurate estimates for energy and area and show a significant energy improvement over a conventional mobile CPU.
R.h. Klenke - One of the best experts on this subject based on the ideXlab platform.
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A new hardware/Software Codesign environment and senior capstone design project for computer engineering
Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03, 2003Co-Authors: R.h. Klenke, J.h. Tucker, Blevins JmAbstract:This paper describes a design environment and platform developed to support senior capstone design projects in computer engineering that incorporates the concept of hardware/Software Codesign. A proposed capstone design project which utilizes this environment is also presented. This project is being undertaken by senior computer engineering students for the first time this year at the authors' university.
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MSE - A new hardware/Software Codesign environment and senior capstone design project for computer engineering
Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03, 2003Co-Authors: R.h. Klenke, J.h. Tucker, Blevins JmAbstract:This paper describes a design environment and platform developed to support senior capstone design projects in computer engineering that incorporates the concept of hardware/Software Codesign. A proposed capstone design project which utilizes this environment is also presented. This project is being undertaken by senior computer engineering students for the first time this year at the authors' university.
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A hardware/Software Codesign senior capstone design project in computer engineering
Proceedings 2001 International Conference on Microelectronic Systems Education, 2001Co-Authors: R.h. KlenkeAbstract:This paper describes a senior capstone design project in computer engineering that incorporates the concept of hardware/ Software Codesign. Details of the project, required infrastructure and tools, and results of the first implementation of this project are described.
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a hardware Software Codesign senior capstone design project in computer engineering
Microelectronics Systems Education, 2001Co-Authors: R.h. KlenkeAbstract:This paper describes a senior capstone design project in computer engineering that incorporates the concept of hardware/ Software Codesign. Details of the project, required infrastructure and tools, and results of the first implementation of this project are described.
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MSE - A hardware/Software Codesign senior capstone design project in computer engineering
Proceedings 2001 International Conference on Microelectronic Systems Education, 2001Co-Authors: R.h. KlenkeAbstract:This paper describes a senior capstone design project in computer engineering that incorporates the concept of hardware/ Software Codesign. Details of the project, required infrastructure and tools, and results of the first implementation of this project are described.
Abhishek Agrawal - One of the best experts on this subject based on the ideXlab platform.
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hardware Software Codesign to optimize soc device battery life
IEEE Computer, 2013Co-Authors: Grace Metri, Manuj Sabharwal, Sundar Iyer, Abhishek AgrawalAbstract:The emergence of battery-constrained system-on-chip (SoC) devices, such as smartphones and tablets, requires hardware/Software Codesign to optimize battery life. Offloading activities from the processor to specialized engines on the SoC can help reduce power consumption.
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Hardware/Software Codesign to optimize SoC device battery life
Computer, 2013Co-Authors: Grace Metri, Manuj Sabharwal, Sundar Iyer, Abhishek AgrawalAbstract:The emergence of battery-constrained system-on-chip (SoC) devices, such as smartphones and tablets, requires hardware/Software Codesign to optimize battery life. Offloading activities from the processor to specialized engines on the SoC can help reduce power consumption. © 2013 IEEE.
