The Experts below are selected from a list of 24693 Experts worldwide ranked by ideXlab platform

Deming Chen - One of the best experts on this subject based on the ideXlab platform.

  • high level synthesis productivity performance and Software constraints
    Journal of Electrical and Computer Engineering, 2012
    Co-Authors: Yun Liang, Kyle Rupnow, Yinan Li, Minh N Do, Deming Chen
    Abstract:

    FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high--often an order of magnitude larger than design effort using high-level languages. Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC. Such tools reduce design effort: high-level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from Software Designer knowledge of the implementation platform. In this paper, we present an unbiased study of the performance, usability and productivity of HLS using AutoPilot (a state-of-the-art HLS tool). In particular, we first evaluate AutoPilot using the popular embedded benchmark kernels. Then, to evaluate the suitability of HLS on real-world applications, we perform a case study of stereo matching, an active area of computer vision research that uses techniques also common for image denoising, image retrieval, feature matching, and face recognition. Based on our study, we provide insights on current limitations of mapping general-purpose Software to hardware using HLS and some future directions for HLS tool development. We also offer several guidelines for hardware-friendly Software design. For popular embedded benchmark kernels, the designs produced by HLS achieve 4× to 126× speedup over the Software version. The stereo matching algorithms achieve between 3.5× and 67.9× speedup over Software (but still less than manual RTL design) with a fivefold reduction in design effort versus manual RTL design.

  • High level synthesis of stereo matching: Productivity, performance, and Software constraints
    2011 International Conference on Field-Programmable Technology, 2011
    Co-Authors: Kyle Rupnow, Minh Do, Dongbo Min, Yinan Li, Yun Liang, Deming Chen
    Abstract:

    FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high - often an order of magnitude larger than design effort using high level languages. Instead of this time-consuming process, high level synthesis (HLS) tools generate hardware implementations from high level languages (HLL) such as C/C++/SystemC. Such tools reduce design effort: high level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from Software Designer knowledge of the implementation platform. In this paper, we examine several implementations of stereo matching, an active area of computer vision research that uses techniques also common for image de-noising, image retrieval, feature matching and face recognition. We present an unbiased evaluation of the suitability of using HLS for typical stereo matching Software, usability and productivity of AutoPilot (a state of the art HLS tool), and the performance of designs produced by AutoPilot. Based on our study, we provide guidelines for Software design, limitations of mapping general purpose Software to hardware using HLS, and future directions for HLS tool development. For the stereo matching algorithms, we demonstrate between 3.5X and 67.9X speedup over Software (but less than achievable by manual RTL design) with a five-fold reduction in design effort vs. manual hardware design.

Yun Liang - One of the best experts on this subject based on the ideXlab platform.

  • high level synthesis productivity performance and Software constraints
    Journal of Electrical and Computer Engineering, 2012
    Co-Authors: Yun Liang, Kyle Rupnow, Yinan Li, Minh N Do, Deming Chen
    Abstract:

    FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high--often an order of magnitude larger than design effort using high-level languages. Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC. Such tools reduce design effort: high-level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from Software Designer knowledge of the implementation platform. In this paper, we present an unbiased study of the performance, usability and productivity of HLS using AutoPilot (a state-of-the-art HLS tool). In particular, we first evaluate AutoPilot using the popular embedded benchmark kernels. Then, to evaluate the suitability of HLS on real-world applications, we perform a case study of stereo matching, an active area of computer vision research that uses techniques also common for image denoising, image retrieval, feature matching, and face recognition. Based on our study, we provide insights on current limitations of mapping general-purpose Software to hardware using HLS and some future directions for HLS tool development. We also offer several guidelines for hardware-friendly Software design. For popular embedded benchmark kernels, the designs produced by HLS achieve 4× to 126× speedup over the Software version. The stereo matching algorithms achieve between 3.5× and 67.9× speedup over Software (but still less than manual RTL design) with a fivefold reduction in design effort versus manual RTL design.

  • High level synthesis of stereo matching: Productivity, performance, and Software constraints
    2011 International Conference on Field-Programmable Technology, 2011
    Co-Authors: Kyle Rupnow, Minh Do, Dongbo Min, Yinan Li, Yun Liang, Deming Chen
    Abstract:

    FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high - often an order of magnitude larger than design effort using high level languages. Instead of this time-consuming process, high level synthesis (HLS) tools generate hardware implementations from high level languages (HLL) such as C/C++/SystemC. Such tools reduce design effort: high level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from Software Designer knowledge of the implementation platform. In this paper, we examine several implementations of stereo matching, an active area of computer vision research that uses techniques also common for image de-noising, image retrieval, feature matching and face recognition. We present an unbiased evaluation of the suitability of using HLS for typical stereo matching Software, usability and productivity of AutoPilot (a state of the art HLS tool), and the performance of designs produced by AutoPilot. Based on our study, we provide guidelines for Software design, limitations of mapping general purpose Software to hardware using HLS, and future directions for HLS tool development. For the stereo matching algorithms, we demonstrate between 3.5X and 67.9X speedup over Software (but less than achievable by manual RTL design) with a five-fold reduction in design effort vs. manual hardware design.

Kyle Rupnow - One of the best experts on this subject based on the ideXlab platform.

  • high level synthesis productivity performance and Software constraints
    Journal of Electrical and Computer Engineering, 2012
    Co-Authors: Yun Liang, Kyle Rupnow, Yinan Li, Minh N Do, Deming Chen
    Abstract:

    FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high--often an order of magnitude larger than design effort using high-level languages. Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC. Such tools reduce design effort: high-level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from Software Designer knowledge of the implementation platform. In this paper, we present an unbiased study of the performance, usability and productivity of HLS using AutoPilot (a state-of-the-art HLS tool). In particular, we first evaluate AutoPilot using the popular embedded benchmark kernels. Then, to evaluate the suitability of HLS on real-world applications, we perform a case study of stereo matching, an active area of computer vision research that uses techniques also common for image denoising, image retrieval, feature matching, and face recognition. Based on our study, we provide insights on current limitations of mapping general-purpose Software to hardware using HLS and some future directions for HLS tool development. We also offer several guidelines for hardware-friendly Software design. For popular embedded benchmark kernels, the designs produced by HLS achieve 4× to 126× speedup over the Software version. The stereo matching algorithms achieve between 3.5× and 67.9× speedup over Software (but still less than manual RTL design) with a fivefold reduction in design effort versus manual RTL design.

  • High level synthesis of stereo matching: Productivity, performance, and Software constraints
    2011 International Conference on Field-Programmable Technology, 2011
    Co-Authors: Kyle Rupnow, Minh Do, Dongbo Min, Yinan Li, Yun Liang, Deming Chen
    Abstract:

    FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high - often an order of magnitude larger than design effort using high level languages. Instead of this time-consuming process, high level synthesis (HLS) tools generate hardware implementations from high level languages (HLL) such as C/C++/SystemC. Such tools reduce design effort: high level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from Software Designer knowledge of the implementation platform. In this paper, we examine several implementations of stereo matching, an active area of computer vision research that uses techniques also common for image de-noising, image retrieval, feature matching and face recognition. We present an unbiased evaluation of the suitability of using HLS for typical stereo matching Software, usability and productivity of AutoPilot (a state of the art HLS tool), and the performance of designs produced by AutoPilot. Based on our study, we provide guidelines for Software design, limitations of mapping general purpose Software to hardware using HLS, and future directions for HLS tool development. For the stereo matching algorithms, we demonstrate between 3.5X and 67.9X speedup over Software (but less than achievable by manual RTL design) with a five-fold reduction in design effort vs. manual hardware design.

Ming-chao Chiang - One of the best experts on this subject based on the ideXlab platform.

  • A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011
    Co-Authors: Ming-chao Chiang, Tse-chen Yeh, Guo-fu Tseng
    Abstract:

    In this paper, we present a fast cycle-accurate instruction set simulator (CA-ISS) for system-on-chip development based on QEMU and SystemC. Even though most state-of-the-art commercial tools have tried very hard to provide all the levels of details to satisfy the different requirements of the Software Designer, the hardware Designer, and even the system architect, the hardware/Software co-simulation speed is dramatically slow when co-simulating the hardware models at the register-transfer level (RTL) with a full-fledged operating system (OS). Our experimental results show that the combination of QEMU and SystemC can make the co-simulation at the CA level much faster than the conventional RTL simulation, even with a full-fledged operating system up and running. Furthermore, the statistics indicate that with every instruction executed and every memory accessed since power-on traced at the CA level, it takes 28m15.804s on average to boot up a full-fledged Linux kernel, even on a personal computer. Compared to the kernel boot time reported by Xilinx and SiCortex, the proposed CA-ISS is about 6.09 times faster compared to “SystemC without trace” of Xilinx and about 30.32 times faster compared to “SystemC models converted from RTL” of SiCortex. The main contributions of this paper are threefold: 1) a hardware/Software co-simulation environment capable of running a full-fledged OS at the early stage of the electronic system level design flow at an acceptable simulation speed is proposed; 2) a virtual platform constructed using the proposed CA-ISS as the processor model can be used to estimate the performance of a target system from system perspective, which all the previous works, such as QEMU-SystemC, do not provide; and 3) such a virtual platform also provides the modeling capability from the transaction level down to the CA level or the other way around.

  • A fast cycle-accurate instruction set simulator based on QEMU and SystemC for SoC development
    Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference, 2010
    Co-Authors: Tse-chen Yeh, Guo-fu Tseng, Ming-chao Chiang
    Abstract:

    This paper presents a fast cycle-accurate instruction set simulator (CA-ISS) based on QEMU and SystemC. The CA-ISS can be used for design space exploration and as the processor core for virtual platform construction at the cycle-accurate level. Even though most state-of-the-art commercial tools try to provide all the levels of details to satisfy the different requirements of the Software Designer, the hardware Designer, or even the system architect, the hardware/Software co-simulation speed is dramatically slow when co-simulating the hardware models at the register-transfer level with a full-fledged operating system. In this paper, we show that the combination of QEMU and SystemC can make the co-simulation at the cycle-accurate level extremely fast, even with a full-fledged operating system up and running. Our experimental results indicate that with every instruction executed and every memory accessed since power-on traced at the cycle-accurate level, it takes less than 17 minutes on average to boot up a full-fledged Linux kernel, even on a laptop.

Yinan Li - One of the best experts on this subject based on the ideXlab platform.

  • high level synthesis productivity performance and Software constraints
    Journal of Electrical and Computer Engineering, 2012
    Co-Authors: Yun Liang, Kyle Rupnow, Yinan Li, Minh N Do, Deming Chen
    Abstract:

    FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high--often an order of magnitude larger than design effort using high-level languages. Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC. Such tools reduce design effort: high-level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from Software Designer knowledge of the implementation platform. In this paper, we present an unbiased study of the performance, usability and productivity of HLS using AutoPilot (a state-of-the-art HLS tool). In particular, we first evaluate AutoPilot using the popular embedded benchmark kernels. Then, to evaluate the suitability of HLS on real-world applications, we perform a case study of stereo matching, an active area of computer vision research that uses techniques also common for image denoising, image retrieval, feature matching, and face recognition. Based on our study, we provide insights on current limitations of mapping general-purpose Software to hardware using HLS and some future directions for HLS tool development. We also offer several guidelines for hardware-friendly Software design. For popular embedded benchmark kernels, the designs produced by HLS achieve 4× to 126× speedup over the Software version. The stereo matching algorithms achieve between 3.5× and 67.9× speedup over Software (but still less than manual RTL design) with a fivefold reduction in design effort versus manual RTL design.

  • High level synthesis of stereo matching: Productivity, performance, and Software constraints
    2011 International Conference on Field-Programmable Technology, 2011
    Co-Authors: Kyle Rupnow, Minh Do, Dongbo Min, Yinan Li, Yun Liang, Deming Chen
    Abstract:

    FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high - often an order of magnitude larger than design effort using high level languages. Instead of this time-consuming process, high level synthesis (HLS) tools generate hardware implementations from high level languages (HLL) such as C/C++/SystemC. Such tools reduce design effort: high level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from Software Designer knowledge of the implementation platform. In this paper, we examine several implementations of stereo matching, an active area of computer vision research that uses techniques also common for image de-noising, image retrieval, feature matching and face recognition. We present an unbiased evaluation of the suitability of using HLS for typical stereo matching Software, usability and productivity of AutoPilot (a state of the art HLS tool), and the performance of designs produced by AutoPilot. Based on our study, we provide guidelines for Software design, limitations of mapping general purpose Software to hardware using HLS, and future directions for HLS tool development. For the stereo matching algorithms, we demonstrate between 3.5X and 67.9X speedup over Software (but less than achievable by manual RTL design) with a five-fold reduction in design effort vs. manual hardware design.