The Experts below are selected from a list of 120 Experts worldwide ranked by ideXlab platform

N E Murphy - One of the best experts on this subject based on the ideXlab platform.

  • General purpose data acquisition and control via the IBM PC Centronics printer port
    Measurement Science and Technology, 1996
    Co-Authors: N E Murphy
    Abstract:

    This paper describes a novel system for acquiring data and controlling equipment via the parallel port of an IBM PC or compatible. An inexpensive circuit and associated computer Software are described which allow up to 256, eight-bit, digital input and output devices, together with eight hardware Interrupt request lines, to be accessed via the Centronics parallel printer port. Programs can access the external devices via a Software Interrupt into a memory resident driver program. This allows all common programming languages to make use of the system. Data transfer speeds of over 40 000 reads/writes per second are achieved. .

Guo Qingwe - One of the best experts on this subject based on the ideXlab platform.

  • Software Interrupt implemented fault injection method in Linux kernel
    Journal of Computer Applications, 2014
    Co-Authors: Guo Qingwe
    Abstract:

    Aiming at the problem of evaluating the dependability of fault-tolerant operating system, a scheme was proposed to inject single-bit faults in the Linux kernel. Based on Software Interrupt technology existing in x86 architecture, a probe point was firstly installed in the timer Interrupt using loadable kernel module. Then the faults data were delivered from user space to kernel space. Finally about 6 700 faults including transient, intermittent and permanent type were conducted targeting four kernel subsystems, i. e. arch, fs, kernel and mm, by means of a C / S fault injecting model. Experiments indicate that compared with arch and fs subsystems, the kernel and mm are more sensitive to faults, the average detection fault coverage reaches 38. 23%. Compared with data segment, the code segment is more sensitive to faults, the average detection fault coverage reaches 73. 49%. This scheme improves the speed and accuracy when evaluating the dependability of faulttolerant operating system.

Joseph Yiu - One of the best experts on this subject based on the ideXlab platform.

  • The Nested Vectored Interrupt Controller and Interrupt Control
    The Definitive Guide to the ARM Cortex-M3 TI, 2010
    Co-Authors: Joseph Yiu
    Abstract:

    The Nested Vectored Interrupt Controller (NVIC) is an integrated part of the Cortex-M3 processor. It is closely linked to the Cortex-M3 CPU core logic. Its control registers can be accessed as memory-mapped devices. This chapter describes the basic Interrupt configuration. The NVIC supports 1–240 external Interrupt inputs which are commonly known as Interrupt request queues (IRQs). Procedures of setting up an Interrupt have been demonstrated with examples. This chapter also throws light on the basic Interrupt configurations with the help of different registers and highlights Software Interrupt and how it can be generated. The chapter ends with a detailed discussion on the Systick Timer which is integrated with the NVIC.

  • Chapter 12 – Advanced Programming Features and System Behavior
    The Definitive Guide to the ARM Cortex-M3, 2007
    Co-Authors: Joseph Yiu
    Abstract:

    Publisher Summary One approach for developing hard fault and NMI handlers is to carry out only the essential tasks inside the handlers, and the rest of the tasks, such as error reporting, can be pended using a separate exception such as PendSV or a Software Interrupt. This helps ensure that the hard fault handler or NMI is small and robust. Furthermore, one should ensure that the NMI and hard fault handler code will not try to use SVC instructions. Since SVC always has lower priority than hard fault and NMI, using SVC in these handlers will cause lockup. This might look simple, but when the application is complex and one calls functions from different files in the NMI and hard fault handler, one might accidentally call a function that contains an SVC instruction. Therefore, before one develops his or her Software, he or she needs to carefully plan the SVC implementation.

Paul William Prickett - One of the best experts on this subject based on the ideXlab platform.

  • dspic based advanced data acquisition system for monitoring control and security applications
    International Bhurban Conference on Applied Sciences and Technology, 2015
    Co-Authors: Raees A Siddiqui, Roger Ivor Grosvenor, Paul William Prickett
    Abstract:

    This paper reports on design and implementation of data acquisition system based on dsPIC Microcontroller for Monitoring, Control and Security Application. Data acquisition is fundamental stage in any DSP, monitoring and digital control and security system. The efficiency and effectiveness of the system is defined by the quality of acquired data, which in turn depends on the characteristics of data acquisition system. There are two types of data acquisition; (a) digital (b) analog data acquisition, having different characteristics and system requirements. Microchip's dsPIC provides various on-chip integrated modules which enable efficient data acquisition such as 10/12-bit Analog to Digital Convertor (ADC) with up to 1Msps (Million samples per second) sampling rate, simultaneous sampling and various trigger mechanisms, Timers, Input Capture (IC), External (hardware) and Internal (Software) Interrupt and processing capability up to 30 MIPS (Million Instructions Per Second). A system is developed for data acquisition of 16 analog signals with 10/12-bit resolution, simultaneous sampling of 4 signals, fixed and variable sampling rate, on chip storage and real-time signal processing capabilities. The system also supports for data acquisition of digital signals with time resolution of up to 33.33nsec and signal parameters like frequency, time period, pulse width, duty cycle, and delay & time difference between two signals. It can be customized according to the system requirements and provides advanced data acquisition capabilities to the low cost monitoring, control or security system.

N. Zergainoh - One of the best experts on this subject based on the ideXlab platform.

  • Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design
    2003
    Co-Authors: Y. Cho, G. Lee, K. Choi, S. Yoo, N. Zergainoh
    Abstract:

    On-chip communication design includes designing Software parts (operating system, device drivers, Interrupt service routines, etc.) as well as hardware parts (on-chip communication network, communication interfaces of processor/IP/memory, etc.). For an efficient exploration of its design space, we need fast scheduling and timing analysis. In this work, we tackle two problems. One is to incorporate the dynamic behavior of Software (Interrupt processing and context switching) into on-chip-communication scheduing. The other is to reduce on-chip data storage required for on-chip communication, by making different communications to share a physical communication buffer. To solve the problems, we present both integer linear programming formulation and heuristic algorithm.