The Experts below are selected from a list of 3021 Experts worldwide ranked by ideXlab platform
Dejan Markovic - One of the best experts on this subject based on the ideXlab platform.
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A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering
IEEE Journal of Solid-State Circuits, 2013Co-Authors: Vaibhav Karkare, Sarah Gibson, Dejan MarkovicAbstract:Energy-efficient Spike-Sorting DSPs are necessary to allow for the real-time processing of multi-channel, wireless, implantable neural recordings. Online, unsupervised clustering forms an integral part of on-chip Spike Sorting. However, previous Spike-Sorting DSPs did not include unsupervised clustering due to the large memory required for its implementation. We demonstrate the first multi-channel Spike-Sorting DSP chip that includes online, unsupervised clustering. On-chip clustering has been made possible by using a two-stage implementation of an online clustering algorithm, a noise-tolerant distance metric, and selectively clocked high-VT register banks. The 16-channel Spike-Sorting chip, implemented in a 65-nm CMOS process, has a power dissipation of 75 μW at a supply voltage of 270 mV. The implementation of on-chip clustering provides a 240× reduction in the output data rate, which is 3× higher than the data-rate reduction obtained from previous Spike-Sorting DSP chips.
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Spike Sorting: The First Step in Decoding the Brain: The first step in decoding the brain
IEEE Signal Processing Magazine, 2012Co-Authors: Sarah Gibson, Jack W. Judy, Dejan MarkovicAbstract:In this article, we present an overview of the Spike-Sorting problem, its current solutions, and the challenges that remain. Because of the increasing demand for chronically implanted Spike-Sorting hardware, we will also discuss implementation considerations.
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A 75µW, 16-channel neural Spike-Sorting processor with unsupervised clustering
2011Co-Authors: Vaibhav Karkare, Sarah Gibson, Chia-hsiang Yang, Henry Chen, Dejan MarkovicAbstract:We describe a neural Spike-Sorting processor that provides unsupervised clustering simultaneously for 16 channels. The use of a two-stage clustering algorithm, noise-tolerant distance metric, and selectively clocked high-V T register arrays makes online clustering feasible for implementation. The Spike-Sorting processor has a power consumption of 75µW at 270mV and an area of 2.45mm2 in a 65nm CMOS.
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a 130 mu w 64 channel neural Spike Sorting dsp chip
IEEE Journal of Solid-state Circuits, 2011Co-Authors: Vaibhav Karkare, Sarah Gibson, Dejan MarkovicAbstract:Spike Sorting is an important processing step in various neuroscientific and clinical studies. Energy-efficient Spike-Sorting ASICs are necessary to allow real-time processing of multi-channel, wireless neural recordings. Spike-Sorting ASICs have to meet stringent power-density constraints and must provide significant data-rate reduction for wireless transmission. Most existing designs either provide only Spike detection for multi-channel processing, or they provide detection and feature extraction only for a single channel. In this paper, we demonstrate the design of a Spike-Sorting DSP chip that can perform detection, alignment, and feature extraction simultaneously for 64 channels. Spike-Sorting algorithms chosen based on a complexity-performance analysis were implemented on ASIC using a MATLAB/Simulink-based architecture design framework. Energy-delay tradeoffs of the design were analyzed to identify the optimal degree of interleaving. The chip was implemented with a modular architecture, and can be configured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated when the chip is operated to process a reduced number of channels. The chip, implemented in a 90-nm CMOS process, has a power dissipation of 130 μW (power density of 30 μW/mm2) when processing all 64 channels and provides a data-rate reduction of 91.25% (11.71 Mb/s to 1.02 Mb/s).
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A 130- $\mu$ W, 64-Channel Neural Spike-Sorting DSP Chip
IEEE Journal of Solid-State Circuits, 2011Co-Authors: Vaibhav Karkare, Sarah Gibson, Dejan MarkovicAbstract:Spike Sorting is an important processing step in various neuroscientific and clinical studies. Energy-efficient Spike-Sorting ASICs are necessary to allow real-time processing of multi-channel, wireless neural recordings. Spike-Sorting ASICs have to meet stringent power-density constraints and must provide significant data-rate reduction for wireless transmission. Most existing designs either provide only Spike detection for multi-channel processing, or they provide detection and feature extraction only for a single channel. In this paper, we demonstrate the design of a Spike-Sorting DSP chip that can perform detection, alignment, and feature extraction simultaneously for 64 channels. Spike-Sorting algorithms chosen based on a complexity-performance analysis were implemented on ASIC using a MATLAB/Simulink-based architecture design framework. Energy-delay tradeoffs of the design were analyzed to identify the optimal degree of interleaving. The chip was implemented with a modular architecture, and can be configured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated when the chip is operated to process a reduced number of channels. The chip, implemented in a 90-nm CMOS process, has a power dissipation of 130 μW (power density of 30 μW/mm2) when processing all 64 channels and provides a data-rate reduction of 91.25% (11.71 Mb/s to 1.02 Mb/s).
Sarah Gibson - One of the best experts on this subject based on the ideXlab platform.
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A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering
IEEE Journal of Solid-State Circuits, 2013Co-Authors: Vaibhav Karkare, Sarah Gibson, Dejan MarkovicAbstract:Energy-efficient Spike-Sorting DSPs are necessary to allow for the real-time processing of multi-channel, wireless, implantable neural recordings. Online, unsupervised clustering forms an integral part of on-chip Spike Sorting. However, previous Spike-Sorting DSPs did not include unsupervised clustering due to the large memory required for its implementation. We demonstrate the first multi-channel Spike-Sorting DSP chip that includes online, unsupervised clustering. On-chip clustering has been made possible by using a two-stage implementation of an online clustering algorithm, a noise-tolerant distance metric, and selectively clocked high-VT register banks. The 16-channel Spike-Sorting chip, implemented in a 65-nm CMOS process, has a power dissipation of 75 μW at a supply voltage of 270 mV. The implementation of on-chip clustering provides a 240× reduction in the output data rate, which is 3× higher than the data-rate reduction obtained from previous Spike-Sorting DSP chips.
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Neural Spike Sorting in Hardware: From Theory to Practice
2012Co-Authors: Sarah GibsonAbstract:Brain-machine interfaces require real-time, wireless signal acquisition systems. However, wireless transmission of raw data is impossible for high-channel-count systems given the power constraints. Data rates could be reduced, thereby enabling wireless data transmission, by performing Spike Sorting--mapping each recorded action potential to the neuron that generated it--on a DSP at the recording site and transmitting only the Sorting results. Our first objective was to design such a DSP. We first developed a standardized dataset and methodology in order to perform an extensive, unbiased comparison of published Spike-Sorting algorithms to determine which would be most appropriate for hardware implementation. We then considered various implementation issues, such as whether analog or digital Spike detection is more efficient and how best to quantize neural signals. This work led to two low-power digital Spike-Sorting chips. Our second objective was to provide an offline solution for the research setting that would accelerate the processing of data that has already been recorded using conventional data-acquisition systems. Here, we present an FPGA-based Spike-Sorting platform that can increase the speed of offline Spike Sorting by at least 25 times, effectively reducing the time required to sort data from long experiments from several hours to just a few minutes. We attempted to preserve the flexibility of software by implementing several different algorithms in the design, and by providing user control over parameters such as Spike detection thresholds.
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Spike Sorting: The First Step in Decoding the Brain: The first step in decoding the brain
IEEE Signal Processing Magazine, 2012Co-Authors: Sarah Gibson, Jack W. Judy, Dejan MarkovicAbstract:In this article, we present an overview of the Spike-Sorting problem, its current solutions, and the challenges that remain. Because of the increasing demand for chronically implanted Spike-Sorting hardware, we will also discuss implementation considerations.
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A 75µW, 16-channel neural Spike-Sorting processor with unsupervised clustering
2011Co-Authors: Vaibhav Karkare, Sarah Gibson, Chia-hsiang Yang, Henry Chen, Dejan MarkovicAbstract:We describe a neural Spike-Sorting processor that provides unsupervised clustering simultaneously for 16 channels. The use of a two-stage clustering algorithm, noise-tolerant distance metric, and selectively clocked high-V T register arrays makes online clustering feasible for implementation. The Spike-Sorting processor has a power consumption of 75µW at 270mV and an area of 2.45mm2 in a 65nm CMOS.
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a 130 mu w 64 channel neural Spike Sorting dsp chip
IEEE Journal of Solid-state Circuits, 2011Co-Authors: Vaibhav Karkare, Sarah Gibson, Dejan MarkovicAbstract:Spike Sorting is an important processing step in various neuroscientific and clinical studies. Energy-efficient Spike-Sorting ASICs are necessary to allow real-time processing of multi-channel, wireless neural recordings. Spike-Sorting ASICs have to meet stringent power-density constraints and must provide significant data-rate reduction for wireless transmission. Most existing designs either provide only Spike detection for multi-channel processing, or they provide detection and feature extraction only for a single channel. In this paper, we demonstrate the design of a Spike-Sorting DSP chip that can perform detection, alignment, and feature extraction simultaneously for 64 channels. Spike-Sorting algorithms chosen based on a complexity-performance analysis were implemented on ASIC using a MATLAB/Simulink-based architecture design framework. Energy-delay tradeoffs of the design were analyzed to identify the optimal degree of interleaving. The chip was implemented with a modular architecture, and can be configured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated when the chip is operated to process a reduced number of channels. The chip, implemented in a 90-nm CMOS process, has a power dissipation of 130 μW (power density of 30 μW/mm2) when processing all 64 channels and provides a data-rate reduction of 91.25% (11.71 Mb/s to 1.02 Mb/s).
Lianggee Chen - One of the best experts on this subject based on the ideXlab platform.
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ICASSP - Design and implementation of a low power Spike detection processor for 128-channel Spike Sorting microsystem
2014 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), 2014Co-Authors: Tungchien Chen, Lianggee ChenAbstract:It is impractical to apply a general Spike Sorting algorithm for every subject because of the individual characteristics of brain signal. Furthermore, extracting more neural activities for higher accuracy of Spike Sorting requires more input electrodes as well as large power consumption and chip area. Therefore, several practical constraints are considered in this work when implementing a programmable Spike Sorting hardware with large number of input channels. In this paper, we provide a 128-channel Spike detection processor for Spike Sorting microsystem without compromise of the power efficiency. This chip consumes only 87.02uW and 9.7uW/mm 2 of power density, fabricated with 90nm low-leakage CMOS process.
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ICME - Algorithm and implementation of multi-channel Spike Sorting using GPU in a home-care surveillance system
2011 IEEE International Conference on Multimedia and Expo, 2011Co-Authors: Yun-yu Chen, Yi-min Tsai, Lianggee ChenAbstract:Intensive home-care surveillance programs are associated with a marked decrease in the need for hospitalization. They can improve the functional statuses of elderly patients with severe congestive diseases. The GPU-based home-care surveillance system is effective and has a major impact on health expenditure than traditional surveillance equipments. In this work, we propose a Spike Sorting technique as a specific case for the GPU-based home surveillance system. Spike Sorting is the procedure of classifying Spikes corresponding to the firing neurons. In neuroscience research, Spike Sorting is adopted to analyze neural activities, brain functions and sensation. It is also a key component in cortically-controlled neuro-prosthetics for patients. In order to efficiently distinguish different neural Spike activities, a robust Spike Sorting algorithm is required for above applications. To improve accuracy, multi-channel Spike Sorting is necessary. In addition, real-time monitoring for a home-care system is required. Therefore, we exploit a CUDA implementation using GPU for acceleration.
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128 channel Spike Sorting processor with a parallel folding structure in 90nm process
International Symposium on Circuits and Systems, 2009Co-Authors: Tungchien Chen, Wentai Liu, Lianggee ChenAbstract:An emerging class of neural prostheses aims to provide more aggressive performance by realizing advanced realtime signal processing algorithms in particular the Spike Sorting on chips. To support realtime Spike Sorting for 128 channels, the traditional fully parallel approach duplicating 128 processing units results in a large burden on chip area. The fully folding approach sharing one processor over 128 channels consumes large dynamic power in data caching. We propose to use the parallel-folding structure to optimally tradeoff the area and power. Our 128-channel Spike Sorting processor consumes 1.36 mm2 area and 1.87 mW power in 90 nm process. 91.1% and 63.4% of the hardware resources (area×power) are reduced compared to the fully parallel and the fully folding approaches respectively.
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ISCAS - 128-channel Spike Sorting processor with a parallel-folding structure in 90nm process
2009 IEEE International Symposium on Circuits and Systems, 2009Co-Authors: Tungchien Chen, Wentai Liu, Lianggee ChenAbstract:An emerging class of neural prostheses aims to provide more aggressive performance by realizing advanced realtime signal processing algorithms in particular the Spike Sorting on chips. To support realtime Spike Sorting for 128 channels, the traditional fully parallel approach duplicating 128 processing units results in a large burden on chip area. The fully folding approach sharing one processor over 128 channels consumes large dynamic power in data caching. We propose to use the parallel-folding structure to optimally tradeoff the area and power. Our 128-channel Spike Sorting processor consumes 1.36 mm2 area and 1.87 mW power in 90 nm process. 91.1% and 63.4% of the hardware resources (area×power) are reduced compared to the fully parallel and the fully folding approaches respectively.
Alessio Paolo Buccino - One of the best experts on this subject based on the ideXlab platform.
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SpikeInterface, a unified framework for Spike Sorting.
eLife, 2020Co-Authors: Alessio Paolo Buccino, Cole Lincoln Hurwitz, Jeremy F. Magland, Samuel Garcia, Joshua H. Siegle, Roger Hurwitz, Matthias H. HennigAbstract:Much development has been directed towards improving the performance and automation of Spike Sorting. This continuous development, while essential, has contributed to an over-saturation of new, incompatible tools that hinders rigorous benchmarking and complicates reproducible analysis. To address these limitations, we developed SpikeInterface, a Python framework designed to unify preexisting Spike Sorting technologies into a single codebase and to facilitate straightforward comparison and adoption of different approaches. With a few lines of code, researchers can reproducibly run, compare, and benchmark most modern Spike Sorting algorithms; pre-process, post-process, and visualize extracellular datasets; validate, curate, and export Sorting outputs; and more. In this paper, we provide an overview of SpikeInterface and, with applications to real and simulated datasets, demonstrate how it can be utilized to reduce the burden of manual curation and to more comprehensively benchmark automated Spike sorters.
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SpikeInterface, a unified framework for Spike Sorting
2019Co-Authors: Alessio Paolo Buccino, Cole Lincoln Hurwitz, Jeremy F. Magland, Samuel Garcia, Joshua H. Siegle, Roger Hurwitz, Matthias H. HennigAbstract:Much development has been directed towards improving the performance and automation of Spike Sorting. This continuous development, while essential, has contributed to an over-saturation of new, incompatible tools that hinders rigorous benchmarking and complicates reproducible analysis. To address these limitations, we developed SpikeInterface, a Python framework designed to unify preexisting Spike Sorting technologies into a single codebase and to facilitate straightforward comparison and adoption of different approaches. With a few lines of code, researchers can reproducibly run, compare, and benchmark most modern Spike Sorting algorithms; pre-process, post-process, and visualize extracellular datasets; validate, curate, and export Sorting outputs; and more. In this paper, we provide an overview of SpikeInterface and, with applications to real and simulated datasets, demonstrate how it can be utilized to reduce the burden of manual curation and to more comprehensively benchmark automated Spike sorters. With a few lines of code and regardless of the underlying data format, researchers can: run, compare, and benchmark most modern Spike Sorting algorithms; pre-process, post-process, and visualize extracellular datasets; validate, curate, and export Sorting outputs; and more. In this paper, we provide an overview of SpikeInterface and, with applications to both real and simulated extracellular datasets, demonstrate how it can improve the accessibility, reliability, and reproducibility of Spike Sorting in preparation for the widespread use of large-scale electrophysiology.
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independent component analysis for fully automated multi electrode array Spike Sorting
International Conference of the IEEE Engineering in Medicine and Biology Society, 2018Co-Authors: Alessio Paolo Buccino, Espen Hagen, Gaute T Einevoll, Philipp Hafliger, Gert CauwenberghAbstract:In neural electrophysiology, Spike Sorting allows to separate different neurons from extracellularly measured recordings. It is an essential processing step in order to understand neural activity and it is an unsupervised problem in nature, since no ground truth information is available. There are several available Spike Sorting packages, but many of them require a manual intervention to curate the results, which makes the process time consuming and hard to reproduce. Here, we focus on high-density Multi-Electrode Array (MEA) recordings and we present a fully automated pipeline based on Independent Component Analysis (ICA). While ICA has been previously investigated for Spike Sorting, it has never been compared with fully automated state-of-the-art algorithms. We use realistic simulated datasets to compare the Spike Sorting performance in terms of complexity, signal-to-noise ratio, and recording duration. We show that an ICA-based fully automated Spike Sorting approach can be a viable alternative approach due to its precision and robustness, but it needs to be optimized for time constraints and requires sufficient density of electrodes to cover active neurons in the proximity of the MEA.
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EMBC - Independent Component Analysis for Fully Automated Multi-Electrode Array Spike Sorting
Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Inte, 2018Co-Authors: Alessio Paolo Buccino, Espen Hagen, Gaute T Einevoll, Philipp Hafliger, Gert CauwenberghAbstract:In neural electrophysiology, Spike Sorting allows to separate different neurons from extracellularly measured recordings. It is an essential processing step in order to understand neural activity and it is an unsupervised problem in nature, since no ground truth information is available. There are several available Spike Sorting packages, but many of them require a manual intervention to curate the results, which makes the process time consuming and hard to reproduce. Here, we focus on high-density Multi-Electrode Array (MEA) recordings and we present a fully automated pipeline based on Independent Component Analysis (ICA). While ICA has been previously investigated for Spike Sorting, it has never been compared with fully automated state-of-the-art algorithms. We use realistic simulated datasets to compare the Spike Sorting performance in terms of complexity, signal-to-noise ratio, and recording duration. We show that an ICA-based fully automated Spike Sorting approach can be a viable alternative approach due to its precision and robustness, but it needs to be optimized for time constraints and requires sufficient density of electrodes to cover active neurons in the proximity of the MEA.
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Real- Time Spike Sorting for Multi-Electrode Arrays with Online Independent Component Analysis
2018 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2018Co-Authors: Alessio Paolo Buccino, Sheng-hsiou Hsu, Gert CauwenberghsAbstract:When recording neural activity from extracellular electrodes, Spike Sorting is needed to separate the activity of different neurons. Most of the Spike Sorting packages are offline and use all the available data to distinguish the activity of single neurons from the recordings. However, when performing an experiment, it is helpful to monitor the activity of recorded neurons. Real-time Spike Sorting is not a trivial problem and previous approaches usually require the user to manually separate units or an initial offline calibration phase, which can be deleterious in case of non-stationarity of the recordings. In this contribution, we adapted the Online Recursive Independent Component Analysis (ORICA) algorithm for real-time Spike Sorting of high-density Multi-Electrode Array (MEA) data. Our approach, with its recursive implementation and dimensionality reduction, has the potential to cope with non-stationarity of the signals (e.g. caused by electrode drift) and it yields a better representation of the neural data, which facilitates Spike detection and improves the detection accuracy.
Alexander Bertrand - One of the best experts on this subject based on the ideXlab platform.
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SHYBRID: A Graphical Tool for Generating Hybrid Ground-Truth Spiking Data for Evaluating Spike Sorting Performance
Neuroinformatics, 2020Co-Authors: Jasper Wouters, Fabian Kloosterman, Alexander BertrandAbstract:Spike Sorting is the process of retrieving the Spike times of individual neurons that are present in an extracellular neural recording. Over the last decades, many Spike Sorting algorithms have been published. In an effort to guide a user towards a specific Spike Sorting algorithm, given a specific recording setting (i.e., brain region and recording device), we provide an open-source graphical tool for the generation of hybrid ground-truth data in Python. Hybrid ground-truth data is a data-driven modelling paradigm in which Spikes from a single unit are moved to a different location on the recording probe, thereby generating a virtual unit of which the Spike times are known. The tool enables a user to efficiently generate hybrid ground-truth datasets and make informed decisions between Spike Sorting algorithms, fine-tune the algorithm parameters towards the used recording setting, or get a deeper understanding of those algorithms.
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towards online Spike Sorting for high density neural probes using discriminative template matching with suppression of interfering Spikes
Journal of Neural Engineering, 2018Co-Authors: Jasper Wouters, Fabian Kloosterman, Alexander BertrandAbstract:Objective. The process of grouping neuronal Spikes in an extracellular recording according to their neuronal sources, is generally referred to as Spike Sorting. Currently, the use of Spike Sorting is mainly limited to an offline usage, where Spikes are sorted after the data acquisition has been completed. In this paper, we propose a discriminative template matching algorithm for threshold-based Spike Sorting on high-density extracellular data. Such threshold-based Spike Sorting has a low and deterministic algorithmic delay, allowing for fast online Spike Sorting. Approach. At its core, threshold-based Spike Sorting is driven by linear filters. The proposed discriminative template matching filter design algorithm optimizes the output signal-to-peak-interference ratio in a data-driven fashion, assuming the template of the target Spike is available. The latter allows the filter to suppress the Spikes of interfering neurons and to resolve Spike overlap. The data-driven filter design algorithm requires only templates of the target neurons of interest, which can be retrieved, e.g. through a prior clustering on an initial recording. Main results. The proposed discriminative template matching filters are validated on in vivo ground truth data and are shown to provide single-unit activity with good accuracy using a simple thresholding operation on the filter outputs. Significance. The low algorithmic complexity allows for computationally cheap and fast Spike Sorting. Also the proposed filters are guaranteed to be stable and have a deterministic delay. These characteristics make the proposed filter design method a valuable building block for online Spike Sorting, thereby enabling unit activity-based real-time and closed-loop experiments for high-density neural recordings.