The Experts below are selected from a list of 14535 Experts worldwide ranked by ideXlab platform

Chiu-sing Choy - One of the best experts on this subject based on the ideXlab platform.

  • a five Stage Pipeline 204 cycles mb single port sram based deblocking filter for h 264 avc
    IEEE Transactions on Circuits and Systems for Video Technology, 2008
    Co-Authors: Chiu-sing Choy
    Abstract:

    This paper describes the design and VLSI implementation of a highly efficient, single-port SRAM-based deblocking filter. It can achieve 204 cycles/macroblock throughput for H.264/AVC real-time decoding. Several deblocking filter designs in the literature have been compared and the possibility of realizing them in a Pipeline is studied. Eventually we came up with a completely new design which has a five-Stage Pipeline with gated clock to increase system throughput while reducing power. Data hazards and structure hazards, which are the two most critical issues for a Pipelined filter, are analyzed and resolved. Efficient memory organization for both on-chip SRAM and transposition buffers is employed. By using innovative hybrid edge filtering sequence and out-of-order memory update scenario, we obtain zero stall cycle in normal Pipeline flow, making the best out of a Pipelined architecture. Compared with existing designs, our design achieves at least 18% clock cycle reduction, as well as 20% lower power consumption owing to its efficient Pipeline and memory architecture. The total gate count is comparable to other designs in literature without using any expensive two-port or dual-port on-chip SRAMs.

  • A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC
    IEEE Transactions on Circuits and Systems for Video Technology, 2008
    Co-Authors: Chiu-sing Choy
    Abstract:

    This paper describes the design and VLSI implementation of a highly efficient, single-port SRAM-based deblocking filter. It can achieve 204 cycles/macroblock throughput for H.264/AVC real-time decoding. Several deblocking filter designs in the literature have been compared and the possibility of realizing them in a Pipeline is studied. Eventually we came up with a completely new design which has a five-Stage Pipeline with gated clock to increase system throughput while reducing power. Data hazards and structure hazards, which are the two most critical issues for a Pipelined filter, are analyzed and resolved. Efficient memory organization for both on-chip SRAM and transposition buffers is employed. By using innovative hybrid edge filtering sequence and out-of-order memory update scenario, we obtain zero stall cycle in normal Pipeline flow, making the best out of a Pipelined architecture. Compared with existing designs, our design achieves at least 18% clock cycle reduction, as well as 20% lower power consumption owing to its efficient Pipeline and memory architecture. The total gate count is comparable to other designs in literature without using any expensive two-port or dual-port on-chip SRAMs.

Michael P. Flynn - One of the best experts on this subject based on the ideXlab platform.

  • a 9b 1gs s 27mw two Stage Pipeline adc in 45nm soi cmos
    Asian Solid-State Circuits Conference, 2012
    Co-Authors: Jorge Pernillo, Michael P. Flynn
    Abstract:

    A novel, 9b 1GS/s 2-Stage Pipeline ADC architecture enables high performance with a low-gain op-amp and poor accuracy in the sub-ADC comparators. A reduced MDAC gain of two relaxes the op-amp gain and bandwidth requirements by a factor of 5.7. Deliberate and random comparator mismatch set the trip-points in the 2nd Stage flash sub-converter and decouples performance from matching requirements. Digital trimming of a delay chain eliminates mismatch in the sampling paths to provide a simple, low power alternative to a dedicated front-end SAH. The ADC achieves an ENOB of 7.4b at Nyquist, consumes 27mW from a 1.0V supply, yielding an FOM of 160fJ/conversion-step.

  • A 9b 1GS/s 27mW two-Stage Pipeline ADC in 45nm SOI-CMOS
    2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 2012
    Co-Authors: Jorge Pernillo, Michael P. Flynn
    Abstract:

    A novel, 9b 1GS/s 2-Stage Pipeline ADC architecture enables high performance with a low-gain op-amp and poor accuracy in the sub-ADC comparators. A reduced MDAC gain of two relaxes the op-amp gain and bandwidth requirements by a factor of 5.7. Deliberate and random comparator mismatch set the trip-points in the 2nd Stage flash sub-converter and decouples performance from matching requirements. Digital trimming of a delay chain eliminates mismatch in the sampling paths to provide a simple, low power alternative to a dedicated front-end SAH. The ADC achieves an ENOB of 7.4b at Nyquist, consumes 27mW from a 1.0V supply, yielding an FOM of 160fJ/conversion-step.

  • A SAR-Assisted Two-Stage Pipeline ADC
    IEEE Journal of Solid-State Circuits, 2011
    Co-Authors: Chun C. Lee, Michael P. Flynn
    Abstract:

    Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations. On the other hand Pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex. We pro pose a two-Stage Pipeline ADC architecture with a large first-Stage resolution, enabled with the help of a SAR-based sub-ADC. The prototype 12b 50 MS/s ADC achieves an ENOB of 10.4b at Nyquist, and a figure-of-merit of 52 f J/conversion-step. The ADC achieves low-power, high-resolution and high-speed operation without calibration. The ADC is fabricated in 65 nm and 90 nm CMOS and occupies a core area of only 0.16 mm2.

  • a 12b 50ms s 3 5mw sar assisted 2 Stage Pipeline adc
    Symposium on VLSI Circuits, 2010
    Co-Authors: Michael P. Flynn
    Abstract:

    A 12b 50MS/s ADC is presented that Pipelines a first Stage 6b MDAC with a second Stage 7b SAR ADC. The first Stage uses a low-power SAR architecture for the sub-ADC, to achieve the large 6b Stage resolution. A “half-gain” MDAC reduces the output swing and increases the closed-loop bandwidth of the op-amp in the first Stage. This ADC consumes 3.5mW from a 1.3V supply, achieves an ENOB of 10.4b at Nyquist, and an FOM of 52fJ/conversion-step.

Chun C. Lee - One of the best experts on this subject based on the ideXlab platform.

  • A SAR-Assisted Two-Stage Pipeline ADC
    IEEE Journal of Solid-State Circuits, 2011
    Co-Authors: Chun C. Lee, Michael P. Flynn
    Abstract:

    Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations. On the other hand Pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex. We pro pose a two-Stage Pipeline ADC architecture with a large first-Stage resolution, enabled with the help of a SAR-based sub-ADC. The prototype 12b 50 MS/s ADC achieves an ENOB of 10.4b at Nyquist, and a figure-of-merit of 52 f J/conversion-step. The ADC achieves low-power, high-resolution and high-speed operation without calibration. The ADC is fabricated in 65 nm and 90 nm CMOS and occupies a core area of only 0.16 mm2.

Chih-cheng Hsieh - One of the best experts on this subject based on the ideXlab platform.

  • ISCAS - A 40MS/s 12-bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting
    2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019
    Co-Authors: Yung-te Chang, Chih-cheng Hsieh
    Abstract:

    This paper presents a power-efficient 12-bit zero-crossing based (ZBC) successive-approximation register (SAR)-assisted two-Stage Pipeline analog-to-digital converter (ADC). The ZBC's error propagation of conventional multiple Stage Pipeline ADC is solved by using the proposed two-Stage Pipelined architecture with one residue amplification only. Moreover, to avoid the signal polarity dependent overshoot error of ZCB amplification, the adaptive level shifting (ALS) scheme is proposed to provide a constant polarity with a ×3 charge transfer speed improvement compared to the conventional approach. The prototyped ADC is fabricated in 40nm CMOS technology with core area of 0.019mm2. At 0.9V supply voltage and 40MS/s Sampling rate with 1MHZ input, the implemented ADC achieves a SNDR of 62.2dB with corresponding ENOB of 10.04 bits. The resulting figure-of-merit (FoM) is 5.6fJ/conversion-step.

Xiaofeng Wu - One of the best experts on this subject based on the ideXlab platform.

  • A Five-Stage Pipeline Architecture of the Unscented Kalman Filter for System-on-Chip Applications
    IEEE Transactions on Industrial Electronics, 2018
    Co-Authors: Xiaofeng Wu
    Abstract:

    As an increasing number of mobile robotic systems with an ever greater autonomous capability are developed, there is a proportional increase in the demand for fast and accurate state estimation for those systems. For these increasingly complex systems, high performance and light, compact form factors are often opposing forces in design. In addition, there are applications where it may be appropriate to use multiple instances of the system operating in some formation/constellation, which has the potential to further increase the computational load on each individual system. A hardware approach based on a field programmable gate array may be able to miniaturize the state estimation subsystem while retaining the desired high performance but also has a more complex development process compared to traditional software-based designs. Leveraging the advantages of both approaches, a hardware/software co-design of the unscented Kalman filter with a five-Stage Pipeline is presented. Simulated results of the design for a small (five) constellation of nanosatellites are presented as are implementation results (timing, synthesis, and power) on the Zynq-7000 XC7Z045 for the one, two, five, and ten processing element cases. A secondary hardware-in-loop simulation of single 3U CubeSat is also presented.