The Experts below are selected from a list of 282 Experts worldwide ranked by ideXlab platform

Feiqi Deng - One of the best experts on this subject based on the ideXlab platform.

Tianliang Zhang - One of the best experts on this subject based on the ideXlab platform.

Akira Fukuda - One of the best experts on this subject based on the ideXlab platform.

  • Formal semantics of extended hierarchical State Transition Matrix by CSP
    ACM SIGSOFT Software Engineering Notes, 2012
    Co-Authors: Yoriyuki Yamagata, Weiqiang Kong, Akira Fukuda, Van Tang Nguyen, Hitoshi Ohsaki, Kenji Taguchi
    Abstract:

    The Extended Hierarchical State Transition Matrix (EHSTM) is a table-based modeling language frequently used in industry for specifying behaviors of a system. However, assuring correctness, i.e., having a design satisfy certain desired properties, is a non-trivial task. To address this problem, a model checker dedicated to EHSTMs called Garakabu2 is developed. However, there is no formal justification of Garakabu2, since its semantics has never been fully formalized. In this paper, we give a formal semantics to EHSTM by translating it into CSP, Communicating Sequential Processes. Our semantics covers most of the features supported by Garakabu2. We manually translate the small examples of EHSTM to CSP, and verify them by PAT, a CSP based model checker. We also verify the examples directly using Garakabu2 and show the result are same. The experiments also show that verification using our translation and PAT is much faster than that of Garakabu2 for checking message type EHSTM.

  • formal verification of software designs in hierarchical State Transition Matrix with smt based bounded model checking
    Asia-Pacific Software Engineering Conference, 2011
    Co-Authors: Weiqiang Kong, Noriyuki Katahira, Masahiko Watanabe, Tetsuro Katayama, Kenji Hisazumi, Akira Fukuda
    Abstract:

    Hierarchical State Transition Matrix (HSTM) is a table-based modeling language for developing designs of software systems. Although widely used and adopted by (particularly Japanese) software industry, there is still lack of mechanized formal verification supports for conducting rigorous and automatic analysis to improve reliability of HSTM designs. In this paper, we first present a formalization of HSTM designs as State Transition systems. Consequentially, based on this formalization, we propose a symbolic encoding approach, through which correctness of a HSTM design with respect to LTL properties could be represented as Bounded Model Checking (BMC) problems that could be determined by Satisfiability Modulo Theories (SMT) solving. We have implemented our encoding approach in a tool called Garakabu2 with the State-of-the-art SMT solver CVC3 as its back-ended solver. Furthermore, in our preliminary experiments, a conceptually simple but steadily effective way of accelerating SMT solving for HSTM designs is investigated and reported.

  • an smt based approach to bounded model checking of designs in communicating State Transition Matrix
    International Conference on Computational Science and Its Applications, 2011
    Co-Authors: Weiqiang Kong, Noriyuki Katahira, Masahiko Watanabe, Tetsuro Katayama, Wanpeng Qian, Akira Fukuda
    Abstract:

    State Transition Matrix (STM) is a table-based modeling language for developing designs of software systems. Although widely accepted and used in software industry, there is lack of formal verification supports for conducting rigorous analysis to improve reliability of STM designs. In this paper, we present a symbolic encoding approach for STM designs that employ message passing as the means of communication, through which correctness of a STM design with respect to invariant properties could be Bounded Model Checked (BMC) by using Satisfiability Modulo Theories (SMT) solving techniques. We have built a prototype implementation of the proposed encoding and the State-of-the-art SMT solver -- Yices, is used in our experiments as a back-end tool to evaluate the effectiveness of our approach. In addition, two approaches for accelerating SMT solving by introducing additional knowledge are proposed and their effectiveness is shown by our preliminary experimental results.

  • An SMT-Based Approach to Bounded Model Checking of Designs in State Transition Matrix
    IEICE Transactions on Information and Systems, 2011
    Co-Authors: Weiqiang Kong, Tomohiro Shiraishi, Noriyuki Katahira, Masahiko Watanabe, Tetsuro Katayama, Akira Fukuda
    Abstract:

    State Transition Matrix (STM) is a table-based modeling language that has been frequently used in industry for specifying behaviors of systems. Functional correctness of a STM design (i.e., a design developed with STM) could often be expressed as invariant properties. In this paper, we first present a formalization of the static and dynamic aspects of STM designs. Consequentially, based on this formalization, we investigate a symbolic encoding approach, through which a STM design could be bounded model checked w.r.t. invariant properties by using Satisfiability Modulo Theories (SMT) solving technique. We have built a prototype implementation of the proposed encoding and the State-of-the-art SMT solver - Yices, is used in our experiments to evaluate the effectiveness of our approach. Two attempts for accelerating SMT solving are also reported.

  • ICCSA Workshops - An SMT-Based Approach to Bounded Model Checking of Designs in Communicating State Transition Matrix
    2011 International Conference on Computational Science and Its Applications, 2011
    Co-Authors: Weiqiang Kong, Noriyuki Katahira, Masahiko Watanabe, Tetsuro Katayama, Wanpeng Qian, Akira Fukuda
    Abstract:

    State Transition Matrix (STM) is a table-based modeling language for developing designs of software systems. Although widely accepted and used in software industry, there is lack of formal verification supports for conducting rigorous analysis to improve reliability of STM designs. In this paper, we present a symbolic encoding approach for STM designs that employ message passing as the means of communication, through which correctness of a STM design with respect to invariant properties could be Bounded Model Checked (BMC) by using Satisfiability Modulo Theories (SMT) solving techniques. We have built a prototype implementation of the proposed encoding and the State-of-the-art SMT solver -- Yices, is used in our experiments as a back-end tool to evaluate the effectiveness of our approach. In addition, two approaches for accelerating SMT solving by introducing additional knowledge are proposed and their effectiveness is shown by our preliminary experimental results.

Zhang Weihai - One of the best experts on this subject based on the ideXlab platform.

Weiqiang Kong - One of the best experts on this subject based on the ideXlab platform.

  • Formal semantics of extended hierarchical State Transition Matrix by CSP
    ACM SIGSOFT Software Engineering Notes, 2012
    Co-Authors: Yoriyuki Yamagata, Weiqiang Kong, Akira Fukuda, Van Tang Nguyen, Hitoshi Ohsaki, Kenji Taguchi
    Abstract:

    The Extended Hierarchical State Transition Matrix (EHSTM) is a table-based modeling language frequently used in industry for specifying behaviors of a system. However, assuring correctness, i.e., having a design satisfy certain desired properties, is a non-trivial task. To address this problem, a model checker dedicated to EHSTMs called Garakabu2 is developed. However, there is no formal justification of Garakabu2, since its semantics has never been fully formalized. In this paper, we give a formal semantics to EHSTM by translating it into CSP, Communicating Sequential Processes. Our semantics covers most of the features supported by Garakabu2. We manually translate the small examples of EHSTM to CSP, and verify them by PAT, a CSP based model checker. We also verify the examples directly using Garakabu2 and show the result are same. The experiments also show that verification using our translation and PAT is much faster than that of Garakabu2 for checking message type EHSTM.

  • formal verification of software designs in hierarchical State Transition Matrix with smt based bounded model checking
    Asia-Pacific Software Engineering Conference, 2011
    Co-Authors: Weiqiang Kong, Noriyuki Katahira, Masahiko Watanabe, Tetsuro Katayama, Kenji Hisazumi, Akira Fukuda
    Abstract:

    Hierarchical State Transition Matrix (HSTM) is a table-based modeling language for developing designs of software systems. Although widely used and adopted by (particularly Japanese) software industry, there is still lack of mechanized formal verification supports for conducting rigorous and automatic analysis to improve reliability of HSTM designs. In this paper, we first present a formalization of HSTM designs as State Transition systems. Consequentially, based on this formalization, we propose a symbolic encoding approach, through which correctness of a HSTM design with respect to LTL properties could be represented as Bounded Model Checking (BMC) problems that could be determined by Satisfiability Modulo Theories (SMT) solving. We have implemented our encoding approach in a tool called Garakabu2 with the State-of-the-art SMT solver CVC3 as its back-ended solver. Furthermore, in our preliminary experiments, a conceptually simple but steadily effective way of accelerating SMT solving for HSTM designs is investigated and reported.

  • an smt based approach to bounded model checking of designs in communicating State Transition Matrix
    International Conference on Computational Science and Its Applications, 2011
    Co-Authors: Weiqiang Kong, Noriyuki Katahira, Masahiko Watanabe, Tetsuro Katayama, Wanpeng Qian, Akira Fukuda
    Abstract:

    State Transition Matrix (STM) is a table-based modeling language for developing designs of software systems. Although widely accepted and used in software industry, there is lack of formal verification supports for conducting rigorous analysis to improve reliability of STM designs. In this paper, we present a symbolic encoding approach for STM designs that employ message passing as the means of communication, through which correctness of a STM design with respect to invariant properties could be Bounded Model Checked (BMC) by using Satisfiability Modulo Theories (SMT) solving techniques. We have built a prototype implementation of the proposed encoding and the State-of-the-art SMT solver -- Yices, is used in our experiments as a back-end tool to evaluate the effectiveness of our approach. In addition, two approaches for accelerating SMT solving by introducing additional knowledge are proposed and their effectiveness is shown by our preliminary experimental results.

  • An SMT-Based Approach to Bounded Model Checking of Designs in State Transition Matrix
    IEICE Transactions on Information and Systems, 2011
    Co-Authors: Weiqiang Kong, Tomohiro Shiraishi, Noriyuki Katahira, Masahiko Watanabe, Tetsuro Katayama, Akira Fukuda
    Abstract:

    State Transition Matrix (STM) is a table-based modeling language that has been frequently used in industry for specifying behaviors of systems. Functional correctness of a STM design (i.e., a design developed with STM) could often be expressed as invariant properties. In this paper, we first present a formalization of the static and dynamic aspects of STM designs. Consequentially, based on this formalization, we investigate a symbolic encoding approach, through which a STM design could be bounded model checked w.r.t. invariant properties by using Satisfiability Modulo Theories (SMT) solving technique. We have built a prototype implementation of the proposed encoding and the State-of-the-art SMT solver - Yices, is used in our experiments to evaluate the effectiveness of our approach. Two attempts for accelerating SMT solving are also reported.

  • ICCSA Workshops - An SMT-Based Approach to Bounded Model Checking of Designs in Communicating State Transition Matrix
    2011 International Conference on Computational Science and Its Applications, 2011
    Co-Authors: Weiqiang Kong, Noriyuki Katahira, Masahiko Watanabe, Tetsuro Katayama, Wanpeng Qian, Akira Fukuda
    Abstract:

    State Transition Matrix (STM) is a table-based modeling language for developing designs of software systems. Although widely accepted and used in software industry, there is lack of formal verification supports for conducting rigorous analysis to improve reliability of STM designs. In this paper, we present a symbolic encoding approach for STM designs that employ message passing as the means of communication, through which correctness of a STM design with respect to invariant properties could be Bounded Model Checked (BMC) by using Satisfiability Modulo Theories (SMT) solving techniques. We have built a prototype implementation of the proposed encoding and the State-of-the-art SMT solver -- Yices, is used in our experiments as a back-end tool to evaluate the effectiveness of our approach. In addition, two approaches for accelerating SMT solving by introducing additional knowledge are proposed and their effectiveness is shown by our preliminary experimental results.