The Experts below are selected from a list of 7767 Experts worldwide ranked by ideXlab platform
Montserrat Nafria - One of the best experts on this subject based on the ideXlab platform.
-
a versatile cmos transistor array ic for the Statistical Characterization of time zero variability rtn bti and hci
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Javier Diazfortuny, Rosana Rodriguez, Elisenda Roca, Xavier Aragones, Enrique Barajas, Diego Mateo, Francisco V. Fernandez, J Martinmartinez, R Castrolopez, Montserrat NafriaAbstract:Statistical Characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to Statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the Characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for Statistical Characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 $\times $ 1800 $\mu \text{m}^{\mathbf {2}}$ .
-
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
IEEE Journal of Solid-State Circuits, 2019Co-Authors: Javier Diaz-fortuny, Javier Martin-martinez, Rosana Rodriguez, Rafael Castro-lopez, Elisenda Roca, Xavier Aragones, Enrique Barajas, Diego Mateo, Francisco V. Fernandez, Montserrat NafriaAbstract:Statistical Characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to Statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the Characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for Statistical Characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 × 1800 μm2.
J M Hallen - One of the best experts on this subject based on the ideXlab platform.
-
Discussion: Statistical Characterization of Pitting Corrosion—Part 1: Data Analysis and Part 2: Probabilistic Modeling for Maximum Pit Depth
Corrosion, 2020Co-Authors: A Valor, D Rivas, F Caleyo, J M HallenAbstract:Abstract A. Valor, et al., discuss “Statistical Characterization of Pitting Corrosion—Part 1: Data Analysis” and “Statistical Characterization of Pitting Corrosion—Part 2: Probabilistic Modeling for Maximum Pit Depth,” by R.E. Melchers, which were published in Corrosion 61, 7 (2005), p. 655–664 and Corrosion 61, 8 (2005), p. 766–777, respectively. A reply from R.E. Melchers follows.
-
discussion Statistical Characterization of pitting corrosion part 1 data analysis and part 2 probabilistic modeling for maximum pit depth
Corrosion, 2007Co-Authors: A Valor, D Rivas, F Caleyo, J M HallenAbstract:Abstract A. Valor, et al., discuss “Statistical Characterization of Pitting Corrosion—Part 1: Data Analysis” and “Statistical Characterization of Pitting Corrosion—Part 2: Probabilistic Modeling for Maximum Pit Depth,” by R.E. Melchers, which were published in Corrosion 61, 7 (2005), p. 655–664 and Corrosion 61, 8 (2005), p. 766–777, respectively. A reply from R.E. Melchers follows.
Xavier Aragones - One of the best experts on this subject based on the ideXlab platform.
-
a versatile cmos transistor array ic for the Statistical Characterization of time zero variability rtn bti and hci
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Javier Diazfortuny, Rosana Rodriguez, Elisenda Roca, Xavier Aragones, Enrique Barajas, Diego Mateo, Francisco V. Fernandez, J Martinmartinez, R Castrolopez, Montserrat NafriaAbstract:Statistical Characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to Statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the Characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for Statistical Characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 $\times $ 1800 $\mu \text{m}^{\mathbf {2}}$ .
-
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
IEEE Journal of Solid-State Circuits, 2019Co-Authors: Javier Diaz-fortuny, Javier Martin-martinez, Rosana Rodriguez, Rafael Castro-lopez, Elisenda Roca, Xavier Aragones, Enrique Barajas, Diego Mateo, Francisco V. Fernandez, Montserrat NafriaAbstract:Statistical Characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to Statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the Characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for Statistical Characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 × 1800 μm2.
Francisco V. Fernandez - One of the best experts on this subject based on the ideXlab platform.
-
a versatile cmos transistor array ic for the Statistical Characterization of time zero variability rtn bti and hci
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Javier Diazfortuny, Rosana Rodriguez, Elisenda Roca, Xavier Aragones, Enrique Barajas, Diego Mateo, Francisco V. Fernandez, J Martinmartinez, R Castrolopez, Montserrat NafriaAbstract:Statistical Characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to Statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the Characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for Statistical Characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 $\times $ 1800 $\mu \text{m}^{\mathbf {2}}$ .
-
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
IEEE Journal of Solid-State Circuits, 2019Co-Authors: Javier Diaz-fortuny, Javier Martin-martinez, Rosana Rodriguez, Rafael Castro-lopez, Elisenda Roca, Xavier Aragones, Enrique Barajas, Diego Mateo, Francisco V. Fernandez, Montserrat NafriaAbstract:Statistical Characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to Statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the Characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for Statistical Characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 × 1800 μm2.
Diego Mateo - One of the best experts on this subject based on the ideXlab platform.
-
a versatile cmos transistor array ic for the Statistical Characterization of time zero variability rtn bti and hci
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Javier Diazfortuny, Rosana Rodriguez, Elisenda Roca, Xavier Aragones, Enrique Barajas, Diego Mateo, Francisco V. Fernandez, J Martinmartinez, R Castrolopez, Montserrat NafriaAbstract:Statistical Characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to Statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the Characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for Statistical Characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 $\times $ 1800 $\mu \text{m}^{\mathbf {2}}$ .
-
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
IEEE Journal of Solid-State Circuits, 2019Co-Authors: Javier Diaz-fortuny, Javier Martin-martinez, Rosana Rodriguez, Rafael Castro-lopez, Elisenda Roca, Xavier Aragones, Enrique Barajas, Diego Mateo, Francisco V. Fernandez, Montserrat NafriaAbstract:Statistical Characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to Statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the Characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for Statistical Characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 × 1800 μm2.
