The Experts below are selected from a list of 9 Experts worldwide ranked by ideXlab platform

Douglas Taylor - One of the best experts on this subject based on the ideXlab platform.

  • VHDL Made Easy
    1996
    Co-Authors: David Pellerin, Douglas Taylor
    Abstract:

    Preface. What This Book Is. Who Can Use This Book. Coding Styles. The Companion CD-ROM. Acknowledgments. 1. Introduction. Goals of This Book. What Is VHDL? A Brief History of VHDL. How Is VHDL Used? The FPGA/ASIC Design Process. When Should You Use VHDL? When Should You Not Use VHDL? What About Verilog? What About PLD Languages? 2. A First Look At VHDL. Simple Example: A Comparator. Comparator Source File. Entities and Architectures. Entity Declaration. Architecture Declaration And Body. Data Types. Design Units. Structure Of A Small Design. More Typical Design Description. Levels of Abstraction (Styles). Sample Circuit. Comparator. Shifter (Entity). Concurrent and Sequential VHDL. Signals and Variables. Using a Procedure to Describe Registers. Using a Component to Describe Registers. Structural VHDL. Test Benches. Sample Test Bench. What We've Learned So Far. 3. Exploring Objects and Data Types. Signals. Variables. Constants. Literals. Types and Subtypes. Scalar Types. Composite Types. Operators. Attributes. Type Conversions and Type Marks. Resolved and Unresolved Types. 4. Using Standard Logic. IEEE Standard 1164. Advantages of IEEE 1164. Using The Standard Logic Package. Std_logic_vector and Std_ulogic_vector. Type Conversion and Standard Logic. Standard Logic Data Types. Standard Logic Operators. Standard Logic Type Conversion Functions. Strength Stripping Functions. Edge Detection Functions. Miscellaneous Checking Functions. Standard 1076.3 (the Numeric Standard). Using Numeric Data Types. Numeric Standard Types: Unsigned and Signed. Numeric Standard Operators. Numeric Array Resize Functions. Numeric Type Conversion Functions. 5. Understanding Concurrent Statements. The Concurrent Area. Concurrent Signal Assignments. Conditional Signal Assignment. Selected Signal Assignment. Conditional vs. Selected Assignment. Procedure Calls. Generate Statements. Concurrent Processes. Component Instantiations. Delay Specifications. Signal Drivers. 6. Understanding Sequential Statements. The Process Statement. Using Processes for Combinational Logic. Using Processes for Registered Logic. Using Processes for State Machines. Specifying State Machine Encodings. Using Processes for Test Stimulus. Sequential Statements in Subprograms. Signal and Variable Assignments. If- Then-Else Statements. Case Statements. Loops. Loop Termination. 7. Creating Modular Designs. Functions and Procedures. Functions. Procedures. Parameter Types. Mapping of Parameters. 8. Partitioning Your Design. Blocks. Guarded Blocks. Packages. Package Bodies. Design Libraries. Package Visibility. Components. Mapping of Ports. Generics. Configurations. 9. Writing Test Benches. A Simple Test Bench. Using Assert Statements. Using Loops and Multiple Processes. Writing Test Vectors. Reading and Writing Files with Text I/O. Reading Non-tabular Data from Files. Creating a Test Language. You're On Your Way... Appendix A: Getting The Most Out Of Synthesis. Appendix B: A VITAL Primer. Appendix C: Using VHDL Simulation. Introduction. Design Management. Simulation Features. Understanding Simulation. Loading the Sample Project. Using the Hierarchy Browser. Compiling Modules for Simulation. Linking Modules for Simulation. Using the Accolade Simulator. Summary. Appendix D: Test Bench Generation from Timing Diagrams. Introduction. Background: What is a Test Bench? Automating Test Bench Generation. Tutorial: Generating Test Benches with The WaveFormer. Appendix E: VHDL Keyword List. Appendix F: Driving Game Listings. Appendix G: Synopsys Textio Package. Appendix H: Glossary. Appendix I: Other Resources. Index.

David Pellerin - One of the best experts on this subject based on the ideXlab platform.

  • VHDL Made Easy
    1996
    Co-Authors: David Pellerin, Douglas Taylor
    Abstract:

    Preface. What This Book Is. Who Can Use This Book. Coding Styles. The Companion CD-ROM. Acknowledgments. 1. Introduction. Goals of This Book. What Is VHDL? A Brief History of VHDL. How Is VHDL Used? The FPGA/ASIC Design Process. When Should You Use VHDL? When Should You Not Use VHDL? What About Verilog? What About PLD Languages? 2. A First Look At VHDL. Simple Example: A Comparator. Comparator Source File. Entities and Architectures. Entity Declaration. Architecture Declaration And Body. Data Types. Design Units. Structure Of A Small Design. More Typical Design Description. Levels of Abstraction (Styles). Sample Circuit. Comparator. Shifter (Entity). Concurrent and Sequential VHDL. Signals and Variables. Using a Procedure to Describe Registers. Using a Component to Describe Registers. Structural VHDL. Test Benches. Sample Test Bench. What We've Learned So Far. 3. Exploring Objects and Data Types. Signals. Variables. Constants. Literals. Types and Subtypes. Scalar Types. Composite Types. Operators. Attributes. Type Conversions and Type Marks. Resolved and Unresolved Types. 4. Using Standard Logic. IEEE Standard 1164. Advantages of IEEE 1164. Using The Standard Logic Package. Std_logic_vector and Std_ulogic_vector. Type Conversion and Standard Logic. Standard Logic Data Types. Standard Logic Operators. Standard Logic Type Conversion Functions. Strength Stripping Functions. Edge Detection Functions. Miscellaneous Checking Functions. Standard 1076.3 (the Numeric Standard). Using Numeric Data Types. Numeric Standard Types: Unsigned and Signed. Numeric Standard Operators. Numeric Array Resize Functions. Numeric Type Conversion Functions. 5. Understanding Concurrent Statements. The Concurrent Area. Concurrent Signal Assignments. Conditional Signal Assignment. Selected Signal Assignment. Conditional vs. Selected Assignment. Procedure Calls. Generate Statements. Concurrent Processes. Component Instantiations. Delay Specifications. Signal Drivers. 6. Understanding Sequential Statements. The Process Statement. Using Processes for Combinational Logic. Using Processes for Registered Logic. Using Processes for State Machines. Specifying State Machine Encodings. Using Processes for Test Stimulus. Sequential Statements in Subprograms. Signal and Variable Assignments. If- Then-Else Statements. Case Statements. Loops. Loop Termination. 7. Creating Modular Designs. Functions and Procedures. Functions. Procedures. Parameter Types. Mapping of Parameters. 8. Partitioning Your Design. Blocks. Guarded Blocks. Packages. Package Bodies. Design Libraries. Package Visibility. Components. Mapping of Ports. Generics. Configurations. 9. Writing Test Benches. A Simple Test Bench. Using Assert Statements. Using Loops and Multiple Processes. Writing Test Vectors. Reading and Writing Files with Text I/O. Reading Non-tabular Data from Files. Creating a Test Language. You're On Your Way... Appendix A: Getting The Most Out Of Synthesis. Appendix B: A VITAL Primer. Appendix C: Using VHDL Simulation. Introduction. Design Management. Simulation Features. Understanding Simulation. Loading the Sample Project. Using the Hierarchy Browser. Compiling Modules for Simulation. Linking Modules for Simulation. Using the Accolade Simulator. Summary. Appendix D: Test Bench Generation from Timing Diagrams. Introduction. Background: What is a Test Bench? Automating Test Bench Generation. Tutorial: Generating Test Benches with The WaveFormer. Appendix E: VHDL Keyword List. Appendix F: Driving Game Listings. Appendix G: Synopsys Textio Package. Appendix H: Glossary. Appendix I: Other Resources. Index.

Peter J. Ashenden - One of the best experts on this subject based on the ideXlab platform.

  • New and Changed Operations
    VHDL-2008, 2008
    Co-Authors: Peter J. Ashenden, Jim Lewis
    Abstract:

    This chapter discusses new and changed operations of VHDL (VHSIC hardware description language). In the earlier versions of VHDL, many of the operations were defined in separate standards. In particular, IEEE Std 1164 specified the package std_logic_1164, which defined the types std_ulogic, std_logic, std_ulogic_vector, and Std_logic_vector and the operations on those types. Also, IEEE Std 1076.3 specified the packages numeric_bit and numeric_std, each of which defined the types unsigned and signed and operations on those types. All of these packages are now included as part of the VHDL-2008 standard. VHDL-2008 extends the definition of logical operators to allow them to be used as unary operators. Each such logical reduction operator is applied to a single operand that is an array of bit or Boolean elements and produces a bit or Boolean result, respectively. The std_logic_1164 package also defines overloaded logical reduction operators for std_ulogic_vector operands. VHDL-2008 also provides two new language features that allow us to treat an expression producing a bit or std_ulogic value as a condition. The first of these features is a condition operator, “ ??, ” that converts from a bit or std_ulogic value to a Boolean value. For bit, “??” converts “I” to true and “0” to false. For std_ulogic, “??” converts both “I” and “H” to true and all other values to false. VHDL-2008 extends the definitions of shift operations to include sla and sra in numeric_bit and numeric_std. It also defines all of the shift operations in the new arithmetic packages numeric_bit_unsigned, numeric_std_unsigned, and in the fixed-point packages.

  • Chapter 8 – Standard Packages
    VHDL-2008, 2008
    Co-Authors: Peter J. Ashenden
    Abstract:

    Publisher Summary This chapter summarizes the contents of the packages in VHDL-2008 (VHSIC hardware description language). The VHDL-2008 version of the package defines array/scalar logic operations for std_ulogic and std_ulogic_vector values, mirroring those that are predefined for bit/bit_vector and boolean/boolean_vector. In earlier versions, std_ulogic_vector and Std_logic_vector were declared as separate types. That meant many of the operations had to be declared in two overloaded forms, one for each type. It also made it difficult for us to mix the two types in designs where some signals had multiple resolved sources and others had only a single source. In VHDL-2008, the std_logic_1164 package is revised to take advantage of the new features for resolving elements of composite types. The type Std_logic_vector is now a subtype of std_ulogic_vector. Each of the array operations in the package is defined just for the std_ulogic_vector type and can be applied to Std_logic_vector values. Each of the numeric_bit and numeric_std packages defines the types unsigned and signed, representing binary-coded integers as vectors of bit or std_ulogic elements, as well as operations on these types. VHDL-2008 also provides the numeric_bit_unsigned package. It performs an analogous purpose for bit_vector values, providing the same operations as are provided by numeric_bit for unsigned values. VHDL-2008 defines a number of packages for fixed-point math. The packages are all defined in the library IEEE. For simple cases, fixed-point math amounts to integer math with scaling by a power of 2. The main VHDL-2008 fixed-point package, fixed_generic_pkg, has formal generic constants so that one can choose the rounding and overflow behaviors that are most appropriate for application.

Jim Lewis - One of the best experts on this subject based on the ideXlab platform.

  • New and Changed Operations
    VHDL-2008, 2008
    Co-Authors: Peter J. Ashenden, Jim Lewis
    Abstract:

    This chapter discusses new and changed operations of VHDL (VHSIC hardware description language). In the earlier versions of VHDL, many of the operations were defined in separate standards. In particular, IEEE Std 1164 specified the package std_logic_1164, which defined the types std_ulogic, std_logic, std_ulogic_vector, and Std_logic_vector and the operations on those types. Also, IEEE Std 1076.3 specified the packages numeric_bit and numeric_std, each of which defined the types unsigned and signed and operations on those types. All of these packages are now included as part of the VHDL-2008 standard. VHDL-2008 extends the definition of logical operators to allow them to be used as unary operators. Each such logical reduction operator is applied to a single operand that is an array of bit or Boolean elements and produces a bit or Boolean result, respectively. The std_logic_1164 package also defines overloaded logical reduction operators for std_ulogic_vector operands. VHDL-2008 also provides two new language features that allow us to treat an expression producing a bit or std_ulogic value as a condition. The first of these features is a condition operator, “ ??, ” that converts from a bit or std_ulogic value to a Boolean value. For bit, “??” converts “I” to true and “0” to false. For std_ulogic, “??” converts both “I” and “H” to true and all other values to false. VHDL-2008 extends the definitions of shift operations to include sla and sra in numeric_bit and numeric_std. It also defines all of the shift operations in the new arithmetic packages numeric_bit_unsigned, numeric_std_unsigned, and in the fixed-point packages.