The Experts below are selected from a list of 1071867 Experts worldwide ranked by ideXlab platform
Jim Lewis - One of the best experts on this subject based on the ideXlab platform.
-
New and Changed Operations
VHDL-2008, 2008Co-Authors: Peter J. Ashenden, Jim LewisAbstract:This chapter discusses new and changed operations of VHDL (VHSIC hardware description language). In the earlier versions of VHDL, many of the operations were defined in separate standards. In particular, IEEE Std 1164 specified the package Std_logic_1164, which defined the types std_ulogic, Std_logic, std_ulogic_vector, and Std_logic_vector and the operations on those types. Also, IEEE Std 1076.3 specified the packages numeric_bit and numeric_std, each of which defined the types unsigned and signed and operations on those types. All of these packages are now included as part of the VHDL-2008 standard. VHDL-2008 extends the definition of logical operators to allow them to be used as unary operators. Each such logical reduction operator is applied to a single operand that is an array of bit or Boolean elements and produces a bit or Boolean result, respectively. The Std_logic_1164 package also defines overloaded logical reduction operators for std_ulogic_vector operands. VHDL-2008 also provides two new language features that allow us to treat an expression producing a bit or std_ulogic value as a condition. The first of these features is a condition operator, “ ??, ” that converts from a bit or std_ulogic value to a Boolean value. For bit, “??” converts “I” to true and “0” to false. For std_ulogic, “??” converts both “I” and “H” to true and all other values to false. VHDL-2008 extends the definitions of shift operations to include sla and sra in numeric_bit and numeric_std. It also defines all of the shift operations in the new arithmetic packages numeric_bit_unsigned, numeric_std_unsigned, and in the fixed-point packages.
Peter J. Ashenden - One of the best experts on this subject based on the ideXlab platform.
-
New and Changed Operations
VHDL-2008, 2008Co-Authors: Peter J. Ashenden, Jim LewisAbstract:This chapter discusses new and changed operations of VHDL (VHSIC hardware description language). In the earlier versions of VHDL, many of the operations were defined in separate standards. In particular, IEEE Std 1164 specified the package Std_logic_1164, which defined the types std_ulogic, Std_logic, std_ulogic_vector, and Std_logic_vector and the operations on those types. Also, IEEE Std 1076.3 specified the packages numeric_bit and numeric_std, each of which defined the types unsigned and signed and operations on those types. All of these packages are now included as part of the VHDL-2008 standard. VHDL-2008 extends the definition of logical operators to allow them to be used as unary operators. Each such logical reduction operator is applied to a single operand that is an array of bit or Boolean elements and produces a bit or Boolean result, respectively. The Std_logic_1164 package also defines overloaded logical reduction operators for std_ulogic_vector operands. VHDL-2008 also provides two new language features that allow us to treat an expression producing a bit or std_ulogic value as a condition. The first of these features is a condition operator, “ ??, ” that converts from a bit or std_ulogic value to a Boolean value. For bit, “??” converts “I” to true and “0” to false. For std_ulogic, “??” converts both “I” and “H” to true and all other values to false. VHDL-2008 extends the definitions of shift operations to include sla and sra in numeric_bit and numeric_std. It also defines all of the shift operations in the new arithmetic packages numeric_bit_unsigned, numeric_std_unsigned, and in the fixed-point packages.