The Experts below are selected from a list of 468 Experts worldwide ranked by ideXlab platform
Makinwa K.a.a. - One of the best experts on this subject based on the ideXlab platform.
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A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme
2018Co-Authors: Jiang H., Ligouras C., Nihtianov S., Makinwa K.a.a.Abstract:When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's Summing Node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1
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A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme
2018Co-Authors: Jiang H., Ligouras C., Nihtianov S., Makinwa K.a.a.Abstract:When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's Summing Node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.Accepted Author ManuscriptElectronic InstrumentationMicroelectronic
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A Temperature-to-Digital Converter Based on an Optimized Electrothermal Filter
2009Co-Authors: Kashmiri S.m., Xia S., Makinwa K.a.a.Abstract:This paper describes the design of a CMOS temperature-to-digital converter (TDC). It operates by measuring the temperature-dependent phase shift of an electrothermal filter (ETF). Compared to previous work, this TDC employs an ETF whose layout has been optimized to minimize the thermal phase spread caused by lithographic inaccuracy. To minimize electrical phase spread, the TDC's front-end consists of a wide bandwidth gain-boosted transconductor. The transconductor's output current is then digitized by a phase-domain SigmaDelta modulator whose phase-Summing Node is realized by a chopper demodulator. To minimize the residual offset caused by the demodulator's switching action, the demodulator is located at the virtual ground Nodes established by the transconductor's gain-boosting amplifiers. Measurements on 16 samples (within one batch) show that the TDC has an untrimmed inaccuracy of less than plusmn0.7degC (3sigma) over the military range (-55degC to 125degC)
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A Temperature-to-Digital Converter Based on an Optimized Electrothermal Filter
2009Co-Authors: Kashmiri S.m., Xia S., Makinwa K.a.a.Abstract:This paper describes the design of a CMOS temperature-to-digital converter (TDC). It operates by measuring the temperature-dependent phase shift of an electrothermal filter (ETF). Compared to previous work, this TDC employs an ETF whose layout has been optimized to minimize the thermal phase spread caused by lithographic inaccuracy. To minimize electrical phase spread, the TDC's front-end consists of a wide bandwidth gain-boosted transconductor. The transconductor's output current is then digitized by a phase-domain SigmaDelta modulator whose phase-Summing Node is realized by a chopper demodulator. To minimize the residual offset caused by the demodulator's switching action, the demodulator is located at the virtual ground Nodes established by the transconductor's gain-boosting amplifiers. Measurements on 16 samples (within one batch) show that the TDC has an untrimmed inaccuracy of less than plusmn0.7degC (3sigma) over the military range (-55degC to 125degC).Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Leccese F - One of the best experts on this subject based on the ideXlab platform.
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A simplified cascade controlled channels for a 3 – bits discrete pure linear analog preprocessing folding ADC architecture
2011Co-Authors: Leccese FAbstract:A very simple linear folding architecture for subranging ADC is presented. The preprocessing analog structure is constituted with 2n (with n number of bits) parallel circuits made with a simple subtracting Node and with a series of two MOS switches able to join the functionalities of DAC, Summing Node and amplifier typical of classical subranging ADC. To validate the idea an accurate simulation of the single channels and of the whole structure has been realized
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A simplified 3 –bits discrete pure linear analog preprocessing folding ADC architecture
2008Co-Authors: Leccese FAbstract:A simplified architecture of subranging pure linear folding ADC is proposed. The device is based on the folding idea to eliminate the DAC, the Summing Node and the amplifier, fundamental elements of the classical architecture, replacing them by means of an analogical signal preprocessing parallel structure named “channels”. The presented circuit in addition to the advantage of a reduction of total conversion time than a classical subranging ADC, so approaching ADC flashes, is very simple and easy to build. An accurate simulation of the single channels and of the whole structure validate the idea. A first discrete circuit it has been realized and tested
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New subranging adc architecture for telecommunication systems
2007Co-Authors: Leccese FAbstract:A new architecture of subranging ADC is proposed. Against a little increase of the number of comparators than a classical subranging architecture, the substitution of the DAC and Summing Node brings to a reduction of total conversion time, approaching it to an ADC flash behavior
Kofi A. A. Makinwa - One of the best experts on this subject based on the ideXlab platform.
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a 4 5 nv surd hz capacitively coupled continuous time sigma delta modulator with an energy efficient chopping scheme
2018Co-Authors: Hui Jiang, Costantino Ligouras, Stoyan Nihtianov, Kofi A. A. MakinwaAbstract:When chopping is applied to a continuous-time sigma-delta modulator (CT ${\Sigma \Delta }\text{M}$ ), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator’s feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CT ${\Sigma \Delta }\text{M}$ intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator’s Summing Node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/ ${\surd }$ Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.
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A Temperature-to-Digital Converter Based on an Optimized Electrothermal Filter
2016Co-Authors: Mahdi S. Kashmiri, Student Member, Sha Xia, Kofi A. A. Makinwa, Senior MemberAbstract:Abstract—This paper describes the design of a CMOS tem-perature-to-digital converter (TDC). It operates by measuring the temperature-dependent phase shift of an electrothermal filter (ETF). Compared to previous work, this TDC employs an ETF whose layout has been optimized to minimize the thermal phase spread caused by lithographic inaccuracy. To minimize electrical phase spread, the TDC’s front-end consists of a wide bandwidth gain-boosted transconductor. The transconductor’s output current is then digitized by a phase-domainmodulator whose phase-Summing Node is realized by a chopper demodulator. To minimize the residual offset caused by the demodulator’s switching action, the demodulator is located at the virtual ground Nodes established by the transconductor’s gain-boosting ampli-fiers. Measurements on 16 samples (within one batch) show that the TDC has an untrimmed inaccuracy of less than 0.7 C ( ) over the military range ( 55 C to 125 C). Index Terms—Electrothermal filters, phase-domain sigma-delta modulator, synchronous demodulation, temperature sensors. I
Jiang H. - One of the best experts on this subject based on the ideXlab platform.
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A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme
2018Co-Authors: Jiang H., Ligouras C., Nihtianov S., Makinwa K.a.a.Abstract:When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's Summing Node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1
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A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme
2018Co-Authors: Jiang H., Ligouras C., Nihtianov S., Makinwa K.a.a.Abstract:When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's Summing Node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.Accepted Author ManuscriptElectronic InstrumentationMicroelectronic
Michael Magnone - One of the best experts on this subject based on the ideXlab platform.
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A 3 BITS DISCRETE PURE LINEAR ANALOG PREPROCESSING FOLDING ADC ARCHITECTURE BASED ON CASCADE CONTROLLED CHANNELS
2009Co-Authors: Fabio Leccese, Michael MagnoneAbstract:Abstract − A very simple circuit for a 3-bits discrete pure linear analog preprocessing folding ADC is presented. The device is based on the folding idea: the DAC, the Summing Node and the amplifier, fundamental elements of the classical architecture, are eliminated and replaced with an analogical signal preprocessing parallel structure named “channels”. All channels are connected as a cascade and only three transistors constitute each one. The circuit has been widely analyzed by simulation and its simplicity guarantees easiness of realization, reduction of power consumption and reduction of total conversion time, making it close to the ADC flash. A first discrete circuit it has been realized and tested
