The Experts below are selected from a list of 96 Experts worldwide ranked by ideXlab platform
Tomoaki Yabe - One of the best experts on this subject based on the ideXlab platform.
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a 0 7 v single Supply sram with 0 495 mu m 2 cell in 65 nm technology utilizing self write back sense amplifier and cascaded bit line scheme
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Keiichi Kushida, A Suzuki, G Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Y Takeyama, Tadahiro Sasaki, A Katayama, Yuki Fujimura, Tomoaki YabeAbstract:We proposed a novel SRAM architecture with a high-density cell in low-Supply-voltage Operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-Supply Operation.
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a 0 7v single Supply sram with 0 495um 2 cell in 65nm technology utilizing self write back sense amplifier and cascaded bit line scheme
Symposium on VLSI Circuits, 2008Co-Authors: Keiichi Kushida, A Suzuki, G Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Y Takeyama, Tadahiro Sasaki, A Katayama, Yuki Fujimura, Tomoaki YabeAbstract:A novel SRAM architecture with a high density cell in low Supply voltage Operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single Supply Operation.
Keiichi Kushida - One of the best experts on this subject based on the ideXlab platform.
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a 0 7 v single Supply sram with 0 495 mu m 2 cell in 65 nm technology utilizing self write back sense amplifier and cascaded bit line scheme
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Keiichi Kushida, A Suzuki, G Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Y Takeyama, Tadahiro Sasaki, A Katayama, Yuki Fujimura, Tomoaki YabeAbstract:We proposed a novel SRAM architecture with a high-density cell in low-Supply-voltage Operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-Supply Operation.
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a 0 7v single Supply sram with 0 495um 2 cell in 65nm technology utilizing self write back sense amplifier and cascaded bit line scheme
Symposium on VLSI Circuits, 2008Co-Authors: Keiichi Kushida, A Suzuki, G Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Y Takeyama, Tadahiro Sasaki, A Katayama, Yuki Fujimura, Tomoaki YabeAbstract:A novel SRAM architecture with a high density cell in low Supply voltage Operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single Supply Operation.
G Fukano - One of the best experts on this subject based on the ideXlab platform.
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a 0 7 v single Supply sram with 0 495 mu m 2 cell in 65 nm technology utilizing self write back sense amplifier and cascaded bit line scheme
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Keiichi Kushida, A Suzuki, G Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Y Takeyama, Tadahiro Sasaki, A Katayama, Yuki Fujimura, Tomoaki YabeAbstract:We proposed a novel SRAM architecture with a high-density cell in low-Supply-voltage Operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-Supply Operation.
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a 0 7v single Supply sram with 0 495um 2 cell in 65nm technology utilizing self write back sense amplifier and cascaded bit line scheme
Symposium on VLSI Circuits, 2008Co-Authors: Keiichi Kushida, A Suzuki, G Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Y Takeyama, Tadahiro Sasaki, A Katayama, Yuki Fujimura, Tomoaki YabeAbstract:A novel SRAM architecture with a high density cell in low Supply voltage Operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single Supply Operation.
Atsushi Kawasumi - One of the best experts on this subject based on the ideXlab platform.
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a 0 7 v single Supply sram with 0 495 mu m 2 cell in 65 nm technology utilizing self write back sense amplifier and cascaded bit line scheme
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Keiichi Kushida, A Suzuki, G Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Y Takeyama, Tadahiro Sasaki, A Katayama, Yuki Fujimura, Tomoaki YabeAbstract:We proposed a novel SRAM architecture with a high-density cell in low-Supply-voltage Operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-Supply Operation.
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a 0 7v single Supply sram with 0 495um 2 cell in 65nm technology utilizing self write back sense amplifier and cascaded bit line scheme
Symposium on VLSI Circuits, 2008Co-Authors: Keiichi Kushida, A Suzuki, G Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Y Takeyama, Tadahiro Sasaki, A Katayama, Yuki Fujimura, Tomoaki YabeAbstract:A novel SRAM architecture with a high density cell in low Supply voltage Operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single Supply Operation.
Osamu Hirabayashi - One of the best experts on this subject based on the ideXlab platform.
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a 0 7 v single Supply sram with 0 495 mu m 2 cell in 65 nm technology utilizing self write back sense amplifier and cascaded bit line scheme
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Keiichi Kushida, A Suzuki, G Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Y Takeyama, Tadahiro Sasaki, A Katayama, Yuki Fujimura, Tomoaki YabeAbstract:We proposed a novel SRAM architecture with a high-density cell in low-Supply-voltage Operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-Supply Operation.
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a 0 7v single Supply sram with 0 495um 2 cell in 65nm technology utilizing self write back sense amplifier and cascaded bit line scheme
Symposium on VLSI Circuits, 2008Co-Authors: Keiichi Kushida, A Suzuki, G Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Y Takeyama, Tadahiro Sasaki, A Katayama, Yuki Fujimura, Tomoaki YabeAbstract:A novel SRAM architecture with a high density cell in low Supply voltage Operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single Supply Operation.
