The Experts below are selected from a list of 42 Experts worldwide ranked by ideXlab platform
Arcot Sowmya - One of the best experts on this subject based on the ideXlab platform.
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Synchronous Protocol automata a framework for modelling and verification of soc communication architectures
IEE Proceedings - Computers and Digital Techniques, 2005Co-Authors: Vijay Dsilva, S Ramesh, Arcot SowmyaAbstract:Plug-n-play-style intellectual property reuse in system-on-chip design is facilitated by the use of an on-chip bus architecture. Component integration and verification in such systems is a cumbersome and time consuming process largely concerned with interfacing issues. A Synchronous, finite state machine framework for modelling communication aspects of such architecture is presented. The framework has been developed via interaction with designers and the industry, and is intuitive and light-weight. The development includes cycle-accurate methods for Protocol specification, compatibility verification, interface synthesis and model checking with automated specification. Case studies performed include the AMBA family of Protocols and a proprietary industrial bus Protocol. These modelling exercises show that such models enable reasoning about and comparison of different bus architectures to gain valuable design insights. The utility of this framework is demonstrated by modelling the AMBA bus architecture including details such as pipelined operation, burst transfers, the AHB-APB bridge and arbitration features.
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Synchronous Protocol automata a framework for modelling and verification of soc communication architectures
Design Automation and Test in Europe, 2004Co-Authors: Vijay Dsilva, S Ramesh, Arcot SowmyaAbstract:Plug-n-Play style Intellectual Property (IP) reuse in System on Chip (SoC) design is facilitated by the use of an on-chip bus architecture. We present a Synchronous, Finite State Machine based framework for modelling communication aspects of such architectures. This formalism has been developed via interaction with designers and the industry and is intuitive and lightweight. We have developed cycle accurate methods to formally specify Protocol compatibility and component composition and show how our model can be used for compatibility verification, interface synthesis and model checking with automated specification. We demonstrate the utility of our framework by modelling the AMBA bus architecture including details such as pipelined operation, burst and split transfers, the AHB-APB bridge and arbitration features.
Vijay Dsilva - One of the best experts on this subject based on the ideXlab platform.
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Synchronous Protocol automata a framework for modelling and verification of soc communication architectures
IEE Proceedings - Computers and Digital Techniques, 2005Co-Authors: Vijay Dsilva, S Ramesh, Arcot SowmyaAbstract:Plug-n-play-style intellectual property reuse in system-on-chip design is facilitated by the use of an on-chip bus architecture. Component integration and verification in such systems is a cumbersome and time consuming process largely concerned with interfacing issues. A Synchronous, finite state machine framework for modelling communication aspects of such architecture is presented. The framework has been developed via interaction with designers and the industry, and is intuitive and light-weight. The development includes cycle-accurate methods for Protocol specification, compatibility verification, interface synthesis and model checking with automated specification. Case studies performed include the AMBA family of Protocols and a proprietary industrial bus Protocol. These modelling exercises show that such models enable reasoning about and comparison of different bus architectures to gain valuable design insights. The utility of this framework is demonstrated by modelling the AMBA bus architecture including details such as pipelined operation, burst transfers, the AHB-APB bridge and arbitration features.
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Synchronous Protocol automata a framework for modelling and verification of soc communication architectures
Design Automation and Test in Europe, 2004Co-Authors: Vijay Dsilva, S Ramesh, Arcot SowmyaAbstract:Plug-n-Play style Intellectual Property (IP) reuse in System on Chip (SoC) design is facilitated by the use of an on-chip bus architecture. We present a Synchronous, Finite State Machine based framework for modelling communication aspects of such architectures. This formalism has been developed via interaction with designers and the industry and is intuitive and lightweight. We have developed cycle accurate methods to formally specify Protocol compatibility and component composition and show how our model can be used for compatibility verification, interface synthesis and model checking with automated specification. We demonstrate the utility of our framework by modelling the AMBA bus architecture including details such as pipelined operation, burst and split transfers, the AHB-APB bridge and arbitration features.
Sebastien Tixeuil - One of the best experts on this subject based on the ideXlab platform.
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self stabilization with global rooted synchronizers
International Conference on Distributed Computing Systems, 1998Co-Authors: L O Alima, Joffroy Beauquier, Ajoy K Datta, Sebastien TixeuilAbstract:We propose a self-stabilizing synchronization technique, called the global rooted synchronization, that synchronizes processors in a tree network. This synchronizer converts a Synchronous Protocol for tree networks into a self-stabilizing version. The synchronizer requires only O(1) memory (other than the memory needed to maintain the tree) at each node regardless of the size of the network, stabilizes in O(h) time, where h is the height of the tree, and does not invoice any global operations. Applications of this technique are presented.
S Ramesh - One of the best experts on this subject based on the ideXlab platform.
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Synchronous Protocol automata a framework for modelling and verification of soc communication architectures
IEE Proceedings - Computers and Digital Techniques, 2005Co-Authors: Vijay Dsilva, S Ramesh, Arcot SowmyaAbstract:Plug-n-play-style intellectual property reuse in system-on-chip design is facilitated by the use of an on-chip bus architecture. Component integration and verification in such systems is a cumbersome and time consuming process largely concerned with interfacing issues. A Synchronous, finite state machine framework for modelling communication aspects of such architecture is presented. The framework has been developed via interaction with designers and the industry, and is intuitive and light-weight. The development includes cycle-accurate methods for Protocol specification, compatibility verification, interface synthesis and model checking with automated specification. Case studies performed include the AMBA family of Protocols and a proprietary industrial bus Protocol. These modelling exercises show that such models enable reasoning about and comparison of different bus architectures to gain valuable design insights. The utility of this framework is demonstrated by modelling the AMBA bus architecture including details such as pipelined operation, burst transfers, the AHB-APB bridge and arbitration features.
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Synchronous Protocol automata a framework for modelling and verification of soc communication architectures
Design Automation and Test in Europe, 2004Co-Authors: Vijay Dsilva, S Ramesh, Arcot SowmyaAbstract:Plug-n-Play style Intellectual Property (IP) reuse in System on Chip (SoC) design is facilitated by the use of an on-chip bus architecture. We present a Synchronous, Finite State Machine based framework for modelling communication aspects of such architectures. This formalism has been developed via interaction with designers and the industry and is intuitive and lightweight. We have developed cycle accurate methods to formally specify Protocol compatibility and component composition and show how our model can be used for compatibility verification, interface synthesis and model checking with automated specification. We demonstrate the utility of our framework by modelling the AMBA bus architecture including details such as pipelined operation, burst and split transfers, the AHB-APB bridge and arbitration features.
L O Alima - One of the best experts on this subject based on the ideXlab platform.
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self stabilization with global rooted synchronizers
International Conference on Distributed Computing Systems, 1998Co-Authors: L O Alima, Joffroy Beauquier, Ajoy K Datta, Sebastien TixeuilAbstract:We propose a self-stabilizing synchronization technique, called the global rooted synchronization, that synchronizes processors in a tree network. This synchronizer converts a Synchronous Protocol for tree networks into a self-stabilizing version. The synchronizer requires only O(1) memory (other than the memory needed to maintain the tree) at each node regardless of the size of the network, stabilizes in O(h) time, where h is the height of the tree, and does not invoice any global operations. Applications of this technique are presented.
