The Experts below are selected from a list of 15171 Experts worldwide ranked by ideXlab platform
Nandish Bharat Thaker - One of the best experts on this subject based on the ideXlab platform.
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analysis of use of parity bit for error resilience in case of test data compression technique
2014Co-Authors: Usha Mehta, Rakesh G Trivedi, Nandish Bharat ThakerAbstract:The fault coverage is the major quality criteria for any test data. Any bit flip in test data can reduce the fault coverage and hence yield. As per recent trends, use of preprocessed and compressed test data has been common for testing of IP core based SoC. The bit flip in such data can be more dangerous to fault coverage. Further, the hidden structure of IP core does not allow the System Integrator to analyze the effect of bit flip on fault coverage. In this scenario, it is utmost necessary to make the test data compression method error resilient. In this paper, we have proposed a method to make test data error resilience. Its effect on % compression and test application time is calculated using highly cited ISCAS89 benchmark circuits. Also the on-chip decoder required for error resilient test data is proposed and corresponding results for area-overhead is shown.
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error resilience in case of test data compression technique for ip core based soc
2014Co-Authors: Usha Mehta, Rakesh G Trivedi, Nandish Bharat ThakerAbstract:The fault coverage is the major quality criteria for any test data. Any bit flip in test data can reduce the fault coverage and hence yield. As per recent trends, use of preprocessed and compressed test data has been common for testing of IP core based SoC. The bit flip in such data can be more dangerous to fault coverage. Further, the hidden structure of IP core does not allow the System Integrator to analyze the effect of bit flip on fault coverage. In this scenario, it is utmost necessary to make the test data compression method error resilient. In this paper, we have proposed a method to make test data error resilience. Its effect on % compression and test application time is calculated using highly cited ISCAS89 benchmark circuits. Also the on-chip decoder required for error resilient test data is proposed and corresponding results for area-overhead is shown.
Cuiyan Huang - One of the best experts on this subject based on the ideXlab platform.
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method for detecting goose generic object oriented substation event messages of digital substation
2012Co-Authors: Baofeng Tang, Hui Fan, Xiao Yang, Xiaoyu Wang, Cuiyan HuangAbstract:The invention discloses a method for detecting GOOSE (generic object oriented substation event) messages of a digital substation, comprising the following steps of: firstly, introducing a System Integrator-configured SCD (security coding device) file by a computer procedure, and displaying the GOOSE message contents of IED (intelligent electronic device), which are configured in the SCD file, on a software interface one by one; acquiring GOOSE heartbeat messages of the IED equipment, and displaying the heartbeat messages on the software interface one by one; and automatically comparing the GOOSE information in the SCD file with the acquired GOOSE messages, judging whether the GOOSE information in the SCD file and the acquired GOOSE messages are same or not, and analyzing. The method for automatically detecting the GOOSE messages is provided by using computer language, the introduced SCD file is compared with the captured GOOSE messages, the method can save a large quantity of manpower resources as compared with the prior art, the debugging efficiency of the digital substation can be improved, and the potential safety hazard can be reduced.
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method and System for detecting goose messages of digital substation
2012Co-Authors: Baofeng Tang, Hui Fan, Xiao Yang, Xiaowei Wang, Cuiyan HuangAbstract:A method and System for detecting GOOSE (Generic Object Oriented Substation Event) messages of a digital substation. The method comprises the following steps: firstly, using a computer program to import a SCD (Substation Configuration Description) file configured by a System Integrator, and displaying the GOOSE message contents of an IED (Intelligent Electronic Device) on a software interface item by item, the contents are configured in the SCD file; furthermore, collecting GOOSE heartbeat messages of the IED, and displaying the heartbeat messages on the software interface item by item; finally, automatically comparing the GOOSE information in the SCD file with the collected GOOSE messages, judging whether the two are same or not, and performing an analysis. The method for automatically detecting the GOOSE messages is provided by using a computer language, and the introduced SCD file is compared with the captured GOOSE messages, thus saving a large quantity of manpower resources compared with the prior art, improving the debugging efficiency of the digital substation, and reducing the potential safety hazard.
Burzlaff Fabian - One of the best experts on this subject based on the ideXlab platform.
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Knowledge-driven architecture composition: Assisting the System Integrator to reuse integration knowledge
Springer International Publishing, 2021Co-Authors: Burzlaff Fabian, Bartelt ChristianAbstract:Semantic interoperability for web services is still a problem. Although decentralized solutions such as describing the integration context with a formal mapping language or using a web service description language exist, practitioners rely on implementing software adapters manually. For IoT and Web of Things Systems, current scientific solutions fall short as changing them, once defined, requires strenuous effort. However, devices and thus, their interfaces change often in this class of System. This paper tackles the barrier of high formalization effort for mappings between required and provided interfaces. Therefore, we apply and evaluate a novel integration method for web service choreography. Our empirical experiment shows that this method lowers the integration time and number of errors by assisting the System Integrator to reuse integration knowledge from previous integration cases
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Knowledge-driven architecture composition
2021Co-Authors: Burzlaff FabianAbstract:Service interoperability for embedded devices is a mandatory feature for dynamically changing Internet-of-Things and Industry 4.0 software platforms. Service interoperability is achieved on a technical, syntactic, and semantic level. If service interoperability is achieved on all layers, plug and play functionality known from USB storage sticks or printer drivers becomes feasible. As a result, micro batch size production, individualized automation solution, or job order production become affordable. However, interoperability at the semantic layer is still a problem for the maturing class of IoT Systems. Current solutions to achieve semantic integration of IoT devices’ heterogeneous services include standards, machine-understandable service descriptions, and the implementation of software adapters. Standardization bodies such as the VDMA tackle the problem by providing a reference software architecture and an information meta model for building up domain standards. For instance, the universal machine technology interface (UMATI) facilitates the data exchange between machines, components, installations, and their integration into a customerand user-specific IT ecoSystem for mechanical engineering and plant construction worldwide. Automated component integration approaches fill the gap of software interfaces that are not relying on a global standard. These approaches translate required into provided software interfaces based on the needed architectural styles (e.g., client-server, layered, publish-subscribe, or cloud-based) using additional component descriptions. Interoperability at the semantic layer is achieved by relying on a shared domain vocabulary (e.g., an ontology) and service description (e.g., SAWSDL) used by all devices involved. If these service descriptions are available and machine-understandable knowledge of how to integrate software components on the functional and behavioral level is available, plug and play scenarios are feasible. Both standards and formal service descriptions cannot be applied effectively to IoT Systems as they rely on the assumption that the semantic domain is completely known when they are noted down. This assumption is hard to believe as an increasing number of decentralized developed and connected IoT devices will exist (i.e., 30.73 billion in 2020 and 75.44 billion in 2025). If standards are applied in IoT Systems, they must be updated continuously, so they contain the most recent domain knowledge agreed upon centrally and ahead of application. Although formal descriptions of concrete integration contexts can happen in a decentralized manner, they still rely on the assumption that the knowledge once noted down is complete. Hence, if an interoperable service from a new device is available that has not been considered in the initial integration context, the formal descriptions must be updated continuously. Both the formalization effort and keeping standards up to date result in too much additional engineering effort. Consequently, practitioners rely on implementing software adapters manually. However, this dull solution hardly scales with the increasing number of IoT devices. In this work, we introduce a novel engineering method that explicitly allows for an incomplete semantic domain description without losing the ability for automated IoT System integration. Dropping the completeness claim requires the management of incomplete integration knowledge. By sharing integration knowledge centrally, we assist the System Integrator in automating software adapter generation. In addition to existing approaches, we enable semantic integration for services by making integration knowledge reusable. We empirically show with students that integration effort can be lowered in a home automation context
Francesco Zirpoli - One of the best experts on this subject based on the ideXlab platform.
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supplier involvement in automotive component design outsourcing strategies and supply chain management
International Journal of Technology Management, 2002Co-Authors: Mauro Caputo, Francesco ZirpoliAbstract:In this paper, the analysis is drawn on the motivations, modalities and consequences of supplier involvement in automotive component design. Outsourcing decisions affect the set of core competencies of buyer and supplier and, given certain circumstances, induce a migration of competencies from OEMs to suppliers. An in-depth exploratory multiple case study on a major European car maker and two of its suppliers revealed that this migration of competencies should not threaten the leadership of car makers within the supply chain if it is associated with: (1) a strong competence of the car maker as System Integrator and (2) a new way of conceiving supply chain management.
Usha Mehta - One of the best experts on this subject based on the ideXlab platform.
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analysis of use of parity bit for error resilience in case of test data compression technique
2014Co-Authors: Usha Mehta, Rakesh G Trivedi, Nandish Bharat ThakerAbstract:The fault coverage is the major quality criteria for any test data. Any bit flip in test data can reduce the fault coverage and hence yield. As per recent trends, use of preprocessed and compressed test data has been common for testing of IP core based SoC. The bit flip in such data can be more dangerous to fault coverage. Further, the hidden structure of IP core does not allow the System Integrator to analyze the effect of bit flip on fault coverage. In this scenario, it is utmost necessary to make the test data compression method error resilient. In this paper, we have proposed a method to make test data error resilience. Its effect on % compression and test application time is calculated using highly cited ISCAS89 benchmark circuits. Also the on-chip decoder required for error resilient test data is proposed and corresponding results for area-overhead is shown.
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error resilience in case of test data compression technique for ip core based soc
2014Co-Authors: Usha Mehta, Rakesh G Trivedi, Nandish Bharat ThakerAbstract:The fault coverage is the major quality criteria for any test data. Any bit flip in test data can reduce the fault coverage and hence yield. As per recent trends, use of preprocessed and compressed test data has been common for testing of IP core based SoC. The bit flip in such data can be more dangerous to fault coverage. Further, the hidden structure of IP core does not allow the System Integrator to analyze the effect of bit flip on fault coverage. In this scenario, it is utmost necessary to make the test data compression method error resilient. In this paper, we have proposed a method to make test data error resilience. Its effect on % compression and test application time is calculated using highly cited ISCAS89 benchmark circuits. Also the on-chip decoder required for error resilient test data is proposed and corresponding results for area-overhead is shown.
